https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68232
James Greenhalgh <jgreenhalgh at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2015-11-06
CC| |jgreenhalgh at gcc dot gnu.org
Ever confirmed|0 |1
--- Comment #1 from James Greenhalgh <jgreenhalgh at gcc dot gnu.org> ---
For this testcase to succeed you need a branch cost >= 1. I had thought that
this would cover all targets, but it looks like the ARM target defines branch
target to zero for some configurations.
static int
arm_default_branch_cost (bool speed_p, bool predictable_p ATTRIBUTE_UNUSED)
{
if (TARGET_32BIT)
return (TARGET_THUMB2 && !speed_p) ? 1 : 4;
else
return (optimize > 0) ? 2 : 0;
}
static int
arm_cortex_a5_branch_cost (bool speed_p, bool predictable_p)
{
return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p);
}
/* Thumb-2 branches are relatively cheap on Cortex-M processors ("1 + P
cycles"
on Cortex-M4, where P varies from 1 to 3 according to some criteria),
since
sequences of non-executed instructions in IT blocks probably take the same
amount of time as executed instructions (and the IT instruction itself
takes
space in icache). This function was experimentally determined to give
good
results on a popular embedded benchmark. */
static int
arm_cortex_m_branch_cost (bool speed_p, bool predictable_p)
{
return (TARGET_32BIT && speed_p) ? 1
: arm_default_branch_cost (speed_p, predictable_p);
}
This test should be an XFAIL wherever BRANCH_COST == 0, but I'm not sure what
the polite way to explain that to the test harness is.
Confirmed (and expected) anyway.
