https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113542
Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
Last reconfirmed| |2024-01-24
--- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Options to reproduce
-O2 -mcpu=cortex-m3 -mthumb
The problem is really a back-end issue. But the cause is that the fwprop pass
is now merging
propagating insn 9 into insn 10, replacing:
(set (reg:SI 124 [ _7 ])
(ne:SI (reg:CC 100 cc)
(const_int 0 [0])))
with the flag setting instruction to form
(parallel [
(set (reg:SI 124 [ _7 ])
(ne:SI (reg:SI 122 [ _2 ])
(const_int 0 [0])))
(clobber (reg:CC 100 cc))
])
That's OK, but it means that the combine pass is no-longer able to merge the
flag setter with an earlier result producer.
A similar thing starts to happen arm state this is dropped because the costs
are working out as the same (it has to reduce the cost).
So I think it's that the cost model for thumb2 needs tweaking.
