https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66306
Bug ID: 66306 Summary: ICE in reload Product: gcc Version: 4.8.5 Status: UNCONFIRMED Severity: major Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: krebbel at gcc dot gnu.org Target Milestone: --- Created attachment 35635 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35635&action=edit Reduced testcase cc1plus -O1 t.c ... unsigned int linemap_position_for_loc_and_offset(unsigned int, unsigned int) t.c: In function ‘unsigned int linemap_position_for_loc_and_offset(unsigned int, unsigned int)’: t.c:20:1: internal compiler error: in subst_reloads, at reload.c:6308 } ... t.c.193r.ira: (insn 15 14 16 2 (parallel [ (set (reg:CCL1 33 %cc) (compare:CCL1 (plus:SI (reg:SI 46 [ D.1846 ]) (mem/j:SI (plus:DI (reg/f:DI 44 [ map.0 ]) (const_int 4 [0x4])) [0 map.0_1->ordinary+0 S4 A32])) (reg:SI 46 [ D.1846 ]))) (clobber (scratch:SI)) ]) t.c:15 276 {*addsi3_carry1_cconly} (expr_list:REG_DEAD (reg/f:DI 44 [ map.0 ]) (nil))) Insn 15 is supposed to match the following pattern. Admittedly a nasty combination of a commutative constraint modifier, matching constraints and a scratch register: (define_insn "*add<mode>3_carry1_cconly" [(set (reg CC_REGNUM) (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") (match_operand:GPR 2 "general_operand" "d,d,R,T")) (match_dup 1))) (clobber (match_scratch:GPR 0 "=d,d,d,d"))] "s390_match_ccmode (insn, CCL1mode)" "@ al<g>r\t%0,%2 al<g>rk\t%0,%1,%2 al<g>\t%0,%2 al<y>\t%0,%2" [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") (set_attr "cpu_facility" "*,z196,*,*") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) Reload ends up picking alternative 0 with swapped operands 1 and 2. Unfortunately the reload does not get a reload register assigned and therefore dies with the ICE. Reloads for insn # 15 Reload 0: reload_in (SI) = (mem/j:SI (plus:DI (reg/f:DI 1 %r1 [orig:44 map.0 ] [44]) (const_int 4 [0x4])) [0 map.0_1->ordinary+0 S4 A32]) reload_out (SI) = (scratch:SI) GENERAL_REGS, RELOAD_OTHER (opnum = 0) reload_in_reg: (mem/j:SI (plus:DI (reg/f:DI 1 %r1 [orig:44 map.0 ] [44]) (const_int 4 [0x4])) [0 map.0_1->ordinary+0 S4 A32]) reload_out_reg: (scratch:SI) Regression hunt returns r186861 as the culprit (unfortunately one of my patches :(. However, the patch only seems to reveal the problem since it changes which alternative gets chosen in that example. Even with the patch reverted the same error appears when disabling/removing the other alternatives manually. E.g. by limiting them to higher CPU levels: diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index a875eec..71b2e57 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -4592,7 +4592,7 @@ al<g>\t%0,%2 al<y>\t%0,%2" [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") - (set_attr "cpu_facility" "*,z196,*,*") + (set_attr "cpu_facility" "*,z196,z196,z196") (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik