https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #21 from Bernd Edlinger ---
Author: edlinger
Date: Thu Aug 4 13:23:36 2016
New Revision: 239123
URL: https://gcc.gnu.org/viewcvs?rev=239123=gcc=rev
Log:
016-08-04 Bernd Edlinger
PR
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #20 from Andreas Schwab ---
Works again.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #19 from Bernd Edlinger ---
Created attachment 39036
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=39036=edit
combined patch
Hi,
I've updated the patch again based on Segher's comments.
So that's what I'd like to post on
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #18 from Andreas Schwab ---
With the patches in #16 and #17 bootstrap was successful and the isl testsuite
passes.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #17 from Bernd Edlinger ---
And here an alternative patch for the other paradoxical subreg bug:
Index: cse.c
===
--- cse.c (revision 238891)
+++ cse.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #16 from Bernd Edlinger ---
Alternative patch, that looks like it fixes this issue (but not the other bug).
Note: it generates one instruction more than the first patch, thus
paradoxical subregs trigger at least one other bug, and
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #15 from Bernd Edlinger ---
patch posted here:
https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01742.html
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
James Greenhalgh changed:
What|Removed |Added
CC||zsojka at seznam dot cz
--- Comment
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #13 from Tamar Christina ---
Also successfully bootstrapped on an aarch64 juno board and no regressions.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #12 from Andreas Schwab ---
Sucessfully bootstrapped on aarch64_ilp32 and the ISL testsuite passes.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
Tamar Christina changed:
What|Removed |Added
CC||tamar.christina at arm dot com
---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #10 from Bernd Edlinger ---
(In reply to James Greenhalgh from comment #2)
>
> So I have two questions.
>
> First, where did the DImode paradoxical subreg come from in the first place,
> and why wasn't it a zero-extend?
>
>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
Bernd Edlinger changed:
What|Removed |Added
CC||bernd.edlinger at hotmail dot
de
---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
Andrew Pinski changed:
What|Removed |Added
Keywords||ra
--- Comment #8 from Andrew Pinski
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
Richard Biener changed:
What|Removed |Added
Priority|P3 |P2
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #7 from Andrew Pinski ---
Ok, the one which I was looking into did the correct thing for reload which is
why I was confused. Anyways reload is where the problem is. It is doing a
store of SI mode but then loading it via DI mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #6 from Andrew Pinski ---
(In reply to Andrew Pinski from comment #5)
> Is an invalid combine. GCC must be thinking the upper bits of reg 419 (aka
> 487) was zero for some reason.
No that is fine. In fact reg 487 was done using
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
--- Comment #5 from Andrew Pinski ---
That is the following (I am using ubuntu's 5.3.1 in 1604 right now):
Trying 944, 945 -> 946:
Successfully matched this instruction:
(set (reg:DI 1 x1)
(ior:DI (ashift:DI (reg/f:DI 110 [ obj1$4 ])
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71779
Andrew Pinski changed:
What|Removed |Added
Component|target |rtl-optimization
--- Comment #4 from
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