[Bug target/108185] [RISC-V]RVV assemble not set vsetvli correct.

2023-01-02 Thread jiawei at iscas dot ac.cn via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 --- Comment #3 from jiawei --- (In reply to Kito Cheng from comment #2) > It seems right to me? Yes, It have the same behavior with clang, but it could generate better assemble code like: vl1re8.vv24,0(a0) addi a4,a1,800 vs1r.v

[Bug target/108185] [RISC-V]RVV assemble not set vsetvli correct.

2022-12-29 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #2

[Bug target/108185] [RISC-V]RVV assemble not set vsetvli correct.

2022-12-19 Thread jiawei at iscas dot ac.cn via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 jiawei changed: What|Removed |Added Version|13.0|fortran-dev --- Comment #1 from jiawei ---