[Bug target/40835] redundant comparison instruction

2009-11-23 Thread carrot at google dot com
--- Comment #9 from carrot at google dot com 2009-11-23 08:51 --- Fixed by Richard. Close it. -- carrot at google dot com changed: What|Removed |Added Status|

[Bug target/40835] redundant comparison instruction

2009-11-04 Thread rearnsha at gcc dot gnu dot org
--- Comment #8 from rearnsha at gcc dot gnu dot org 2009-11-04 14:10 --- Subject: Bug 40835 Author: rearnsha Date: Wed Nov 4 14:09:55 2009 New Revision: 153895 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=153895 Log: 2009-11-04 Richard Earnshaw PR target/40835

[Bug target/40835] redundant comparison instruction

2009-07-24 Thread rearnsha at gcc dot gnu dot org
--- Comment #7 from rearnsha at gcc dot gnu dot org 2009-07-24 14:08 --- (In reply to comment #6) > In fact even the compare isn't a separate insn: There's a reason for that. If you separate compares from uses of the flags then reload may end up inserting add or mov instructions in be

[Bug target/40835] redundant comparison instruction

2009-07-24 Thread steven at gcc dot gnu dot org
--- Comment #6 from steven at gcc dot gnu dot org 2009-07-24 08:48 --- In fact even the compare isn't a separate insn: @(insn 6 5 7 t.c:5 (set (reg/v:SI 1 r1 [orig:133 v ] [133]) @(reg:SI 0 r0)) 167 {*thumb1_movsi_insn} (nil)) @ 0x0004 mov r1, r0 @ 6 *thumb1_mov

[Bug target/40835] redundant comparison instruction

2009-07-24 Thread steven at gcc dot gnu dot org
--- Comment #5 from steven at gcc dot gnu dot org 2009-07-24 08:25 --- The fact that the move sets the condition code is not modelled in the insn. >From .expand dump: (insn 6 5 7 3 t.c:5 (set (reg/v:SI 133 [ v ]) (reg:SI 0 r0)) -1 (nil)) >From -dAP output: @(insn 6 5 7 t.c:5 (s

[Bug target/40835] redundant comparison instruction

2009-07-24 Thread carrot at google dot com
--- Comment #4 from carrot at google dot com 2009-07-24 07:37 --- Just as I've figured out HAVE_cc0 is disabled. And cse_condition_code_reg does nothing for thumb target. I also found that the conditional branch instructions is always in the same insn pattern as the previous compare ins

[Bug target/40835] redundant comparison instruction

2009-07-24 Thread steven at gcc dot gnu dot org
--- Comment #3 from steven at gcc dot gnu dot org 2009-07-24 06:59 --- Because HAVE_cc0 is only for cc0 targets, and ARM is not one of those? You should stop jumping to peepholes for every missed optimization you find. There is a csecc pass (part of cse2) that should handle this. You sh

[Bug target/40835] redundant comparison instruction

2009-07-23 Thread carrot at google dot com
--- Comment #2 from carrot at google dot com 2009-07-24 02:11 --- It seems HAVE_cc0 disabled for arm. What's the reason behind it? A simple method is to add a peephole rule to handle it. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40835

[Bug target/40835] redundant comparison instruction

2009-07-23 Thread carrot at google dot com
--- Comment #1 from carrot at google dot com 2009-07-23 08:38 --- Created an attachment (id=18241) --> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=18241&action=view) test case -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40835