https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79203
Bug ID: 79203 Summary: Update PowerPC double->int conversions to know about -mvsx-small-integer Product: gcc Version: 7.0 Status: UNCONFIRMED Severity: enhancement Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: meissner at gcc dot gnu.org Target Milestone: --- In looking at PR 79038, I noticed that the double/float conversions to int/unsigned int were never modified when SImode (32-bit integers) were allowed in vector registers. On power8 and above where SImode can go in vector registers, we should just generate: (set (match_operand:SI 0 "vsx_register_operand" "=wa") (fix:SI (match_operand:DF 1 "vsx_register_operand" "wa"))) instead of: (set (match_operand:DI 0 "vsx_register_operand" "=wa") (unspec:DI [(fix:SI (match_operand:DF 1 "vsx_register_operand" "wa"))] UNSPEC_FCTIWZ)) to hide the SImode from the register allocator. For power7 and earlier, we need the current code, but where SImode can go in the vector registers, we should generate the appropriate code.