https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
Jakub Jelinek changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
--- Comment #8 from Jakub Jelinek ---
Author: jakub
Date: Thu Jan 11 20:49:40 2018
New Revision: 256556
URL: https://gcc.gnu.org/viewcvs?rev=256556=gcc=rev
Log:
PR target/83203
* config/i386/i386.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
Jakub Jelinek changed:
What|Removed |Added
Status|NEW |ASSIGNED
Assignee|unassigned
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
Richard Biener changed:
What|Removed |Added
Priority|P3 |P1
Version|7.2.1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
--- Comment #6 from Richard Biener ---
A general comment from my side here is that RTL really has too many ways to
express vector "combinations" / "shuffles". In particular vec_merge can
be expressed (up to the CONST_INT bitmask limit to 128
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
--- Comment #5 from Uroš Bizjak ---
Also, please note that in the past, new instructions from ISA n+1 were just
bolted to existing patterns without much thought, under assumption that the new
instructions are always faster than the old ones.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
--- Comment #4 from Uroš Bizjak ---
(In reply to Jakub Jelinek from comment #3)
> Now, because this is generic tuning we force that into stack.
> Though I must repeat for the nth time that this is very confusing; either
> for some AMD chips (is
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
Jakub Jelinek changed:
What|Removed |Added
CC||hubicka at gcc dot gnu.org,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
--- Comment #2 from Jakub Jelinek ---
Broken with r254548.
Self-contained testcase:
typedef long long V __attribute__((vector_size (32)));
V
foo (long long x)
{
return (V) { x };
}
I'll have a look.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83203
Richard Biener changed:
What|Removed |Added
Keywords||needs-bisection
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