[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2021-08-02 Thread crazylht at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 --- Comment #10 from Hongtao.liu --- (In reply to Hongtao.liu from comment #9) > Or the backend add combine helper insn to match > > Failed to match this instruction: > (set (reg:V8HI 90) > (rotate:V8HI (reg:V8HI 91) > (const_int 8

[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2021-08-02 Thread crazylht at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 --- Comment #9 from Hongtao.liu --- Or the backend add combine helper insn to match Failed to match this instruction: (set (reg:V8HI 90) (rotate:V8HI (reg:V8HI 91) (const_int 8 [0x8])))

[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2021-08-02 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 Andrew Pinski changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2020-09-04 Thread rguenth at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 --- Comment #7 from Richard Biener --- (In reply to Jakub Jelinek from comment #6) > Or the generic code could try to expand vector rotates by multiplies of > BITS_PER_UNIT as vector permutations, perhaps only if there is no optab for > it. Or

[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2020-09-03 Thread jakub at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 --- Comment #6 from Jakub Jelinek --- Or the generic code could try to expand vector rotates by multiplies of BITS_PER_UNIT as vector permutations, perhaps only if there is no optab for it. Or trying to expand both permutation and rotate and

[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2020-09-03 Thread glisse at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 --- Comment #5 from Marc Glisse --- typedef unsigned short v8i16 __attribute__((vector_size(16))); v8i16 bswap_epi16(v8i16 x) { return (x << 8) | (x >> 8); } We do recognize a rotate already in GENERIC return x r<< 8; But this is

[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2020-09-03 Thread gabravier at gmail dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 --- Comment #4 from Gabriel Ravier --- Oh, now I realise that those headers are actually in fact part of directly GCC-provided headers and not some external package. I must say though, if those functions are internal implementation detail and

[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2020-09-03 Thread jakub at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 Jakub Jelinek changed: What|Removed |Added CC||jakub at gcc dot gnu.org --- Comment #3

[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2020-09-03 Thread gabravier at gmail dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 --- Comment #2 from Gabriel Ravier --- Yes, you can reproduce this with _mm_shuffle_epi8, _mm_slli_epi16 and _mm_srli_epi16. I'm assuming GCC developers are more familiar with the internal intrinsics than with the Intel-provided intrinsics, so I

[Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf

2020-09-03 Thread rguenth at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918 --- Comment #1 from Richard Biener --- Note it's not so interesting to handle testcases with __builtin_ia32_* which are internal but I guess the same can be replicated using intrinsics?