https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
H.J. Lu changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
--- Comment #10 from hjl at gcc dot gnu.org ---
Author: hjl
Date: Thu Jun 20 15:30:54 2019
New Revision: 272511
URL: https://gcc.gnu.org/viewcvs?rev=272511=gcc=rev
Log:
i386: Generate standard floating point scalar operation patterns
Standard
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
H.J. Lu changed:
What|Removed |Added
CC|kirill.yukhin at intel dot com |hjl.tools at gmail dot
com,
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
--- Comment #8 from Marc Glisse glisse at gcc dot gnu.org ---
Just adding a link to the latest message of the conversation, for future
reference:
http://gcc.gnu.org/ml/gcc-patches/2012-12/msg00824.html
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
--- Comment #7 from Marc Glisse glisse at gcc dot gnu.org 2012-11-30 01:31:25
UTC ---
Created attachment 28832
-- http://gcc.gnu.org/bugzilla/attachment.cgi?id=28832
simplify-rtx patch
With the patch, this code takes a single
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
--- Comment #6 from Marc Glisse glisse at gcc dot gnu.org 2012-10-20 17:43:44
UTC ---
Uros' reply at http://gcc.gnu.org/ml/gcc-patches/2012-10/msg01327.html copied
here for convenience:
But, we _do_ have vec_merge pattern that describes
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
--- Comment #2 from Marc Glisse glisse at gcc dot gnu.org 2012-10-12 13:41:35
UTC ---
(In reply to comment #1)
Does not work for + though, as -0.0 + 0.0 is 0.0.
[...]
On the tree level we see in-memory v because of the component
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
--- Comment #3 from Marc Glisse glisse at gcc dot gnu.org 2012-10-12 17:08:20
UTC ---
The following patch gives this loop:
.L7:
subsd%xmm0, %xmm1
subl$1, %eax
addpd%xmm1, %xmm1
jne.L7
I guess I should
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
--- Comment #4 from Marc Glisse glisse at gcc dot gnu.org 2012-10-12 17:33:53
UTC ---
Note that a V4SF version should be doable, since it is 3 insn there as well,
although the pattern is different.
(insn 34 61 36 4 (set (reg:SF 103 [
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
--- Comment #5 from Marc Glisse glisse at gcc dot gnu.org 2012-10-12 18:08:45
UTC ---
Doing the optimization that late is a bit fragile though. For instance:
v[0] += 3.0;
v[0] -= 1.0;
is back to decomposing the vector, doing the
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54855
Richard Guenther rguenth at gcc dot gnu.org changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
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