[Bug bootstrap/97409] riscv cross toolchain build fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97409 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #5

[Bug sanitizer/96307] [10/11 Regression] ICE in sanopt on riscv64 since r11-2283-g2ca1b6d009b194286c3ec91f9c51cc6b0a475458

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96307 Kito Cheng changed: What|Removed |Added Priority|P4 |P3 --- Comment #5 from Kito Cheng ---

[Bug target/96759] [10/11 Regression] ICE in extract_insn, at recog.c:2294

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759 Kito Cheng changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |kito at gcc dot gnu.org

[Bug target/96759] [10/11 Regression] ICE in extract_insn, at recog.c:2294

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759 Kito Cheng changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/98152] [11 regression] /usr/bin/env: 'python': No such file or directory

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98152 Kito Cheng changed: What|Removed |Added Status|NEW |ASSIGNED CC|

[Bug target/98152] [11 regression] /usr/bin/env: 'python': No such file or directory

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98152 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #55 from Kito Cheng --- Hi jiawei: Thanks for the data, the performance changing for coremark-pro seems interesting, could you find which part generate different code after the patch? And I am curious what the platform you used for

[Bug target/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #58 from Kito Cheng --- Hi jiawei: I would suggest you just using inst count rather than cycle or time for measuring benchmark if you using qemu, since qemu is functional simulator not cycle accurate neither nearly-cycle accurate

[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #25 from Kito Cheng --- Seem like you have add code to gcc/optabs.h and gcc/optabs.c, however those functions are RISC-V specific, so I would suggest you put in riscv.c and riscv-protos.h.

[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #37 from Kito Cheng --- Maybe we could add a parameter to indicate the type of memory access, plain_mem, zext_mem or sext_mem for pass_shorten_memrefs::get_si_mem_base_reg. e.g. for (int i = 0; i < 2; i++) {

[Bug target/97682] Miscompiled tail call with -fPIC

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97682 Kito Cheng changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/97682] Miscompiled tail call with -fPIC

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97682 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #11

[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 --- Comment #16 from Kito Cheng --- > Or maybe we make the choice of zero-extend or sign-extend depend on the mode, > and use zero-extend for smaller than SImode and sign-extend for SImode and > larger. Maybe depend on LOAD_EXTEND_OP?

[Bug sanitizer/96307] [10/11 Regression] ICE in sanopt on riscv64 since r11-2283-g2ca1b6d009b194286c3ec91f9c51cc6b0a475458

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96307 --- Comment #7 from Kito Cheng --- Committed fix into trunk, wait one week to commit to gcc 10 branh.

[Bug target/98743] ICE in convert_move, at expr.c:220

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98743 --- Comment #2 from Kito Cheng --- ICE after g:6fbec038f7a7ddf29f074943611b53210d17c40c, hmmm...interesting...

[Bug target/98743] ICE in convert_move, at expr.c:220

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98743 Kito Cheng changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned at

[Bug target/98596] registers not reused on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98596 --- Comment #2 from Kito Cheng --- Few years ago, Monk and me has write a very detailed cost model for nds32 port, that way might able to fix the issue and further optimized for the code size and performance, but...it need lots time to fine tune

[Bug target/98743] ICE in convert_move, at expr.c:220

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98743 --- Comment #3 from Kito Cheng --- Seems like g:3e60ddeb8220ed388819bb3f14e8caa9309fd3c2 is the real root cause

[Bug target/98743] ICE in convert_move, at expr.c:220

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98743 Kito Cheng changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug sanitizer/96307] [10 Regression] ICE in sanopt on riscv64 since r11-2283-g2ca1b6d009b194286c3ec91f9c51cc6b0a475458

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96307 Kito Cheng changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/98878] New: Incorrect multilib list for riscv*-rtems

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98878 Bug ID: 98878 Summary: Incorrect multilib list for riscv*-rtems Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug rtl-optimization/100647] New: ICE during sms pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100647 Bug ID: 100647 Summary: ICE during sms pass Product: gcc Version: 12.0 Status: UNCONFIRMED Keywords: ice-on-valid-code Severity: normal Priority: P3

[Bug target/101275] [RISCV] Document the machine constraint 'S' and make it non-internal

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101275 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #1

[Bug target/98878] Incorrect multilib list for riscv*-rtems

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98878 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug sanitizer/96307] [10 Regression] ICE in sanopt on riscv64 since r11-2283-g2ca1b6d009b194286c3ec91f9c51cc6b0a475458

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96307 --- Comment #12 from Kito Cheng --- > This disables the CC_HAS_KASAN_GENERIC config of the kernel, making KASAN > unavailable. H, I checked with kernel source code, it only feed -fsanitize=kernel-address during checking, but in fact it

[Bug target/99314] [Patch] [RISC-V] g++.dg/opt/memcpy1.C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99314 Kito Cheng changed: What|Removed |Added Status|REOPENED|RESOLVED Resolution|---

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since g:d9f0ade001533c9544bf2153b6baa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702 Kito Cheng changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since r11-7757-gfc9c4e5fc50c7fcbd27d6

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org

[Bug target/99314] [Patch] [RISC-V] g++.dg/opt/memcpy1.C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99314 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug target/99314] [Patch] [RISC-V] g++.dg/opt/memcpy1.C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99314 --- Comment #3 from Kito Cheng --- Thanks for providing environment info, I'll try that soon.

[Bug target/99314] [Patch] [RISC-V] g++.dg/opt/memcpy1.C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99314 Kito Cheng changed: What|Removed |Added Resolution|FIXED |--- Status|RESOLVED

[Bug target/99314] [Patch] [RISC-V] g++.dg/opt/memcpy1.C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99314 --- Comment #1 from Kito Cheng --- I didn't see this testcase failed before, and I can't reproduce that on my work environment, do you mind share your build environment, e.g. the version of gcc or the distribution version?

[Bug target/98981] gcc-10.2 for RISC-V has extraneous register moves

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98981 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #2

[Bug target/101275] [RISCV] Document the machine constraint 'S' and make it non-internal

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101275 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug middle-end/100316] [11/12 Regression] __clear_cache() does not support NULL-pointer arguments

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100316 Kito Cheng changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug middle-end/100316] [11/12 Regression] __clear_cache() does not support NULL-pointer arguments

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100316 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org

[Bug c++/102538] New: Wrong narrowing conversion checking for initializer with union

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102538 Bug ID: 102538 Summary: Wrong narrowing conversion checking for initializer with union Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal

[Bug target/102957] [riscv64] ICE on bogus -march value

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102957 --- Comment #3 from Kito Cheng --- Wait another week for make sure stable and backport to gcc-11 and gcc-10 branch.

[Bug target/102957] [riscv64] ICE on bogus -march value

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102957 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Assignee|unassigned at

[Bug tree-optimization/103603] [11 Regression] stack overflow on ranger for huge program, but OK for legacy

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103603 --- Comment #4 from Kito Cheng --- Hi Andrew: Thanks for your quick response! the patch is work to me for the testcase, but...I got seg fault when I built x86 GCC. Here is a reduced case from gcov, and this testcase also take longer

[Bug tree-optimization/103603] [11 Regression] stack overflow on ranger for huge program, but OK for legacy

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103603 --- Comment #6 from Kito Cheng --- Reported testcase is OK and I test that patch on riscv64-elf and riscv64-linux with full gcc testsuite run, both are no regression.

[Bug tree-optimization/103603] [11 Regression] stack overflow on ranger for huge program, but OK for legacy

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103603 --- Comment #2 from Kito Cheng --- Oh, apologize for misleading, it should fixed via pr103231 rather than pr103254. it work after g:5deacf6058d1bc7261a75c9fd1f116c4442e9e60, no new file, but it's not trivial backport-able.

[Bug target/103525] [RISCV] wrong function entry with -fpatchable-function-entry

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103525 Kito Cheng changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug tree-optimization/103603] New: [11 Regression] stack overflow on ranger for huge program, but OK for legacy

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103603 Bug ID: 103603 Summary: [11 Regression] stack overflow on ranger for huge program, but OK for legacy Product: gcc Version: 11.2.1 Status: UNCONFIRMED

[Bug target/104853] [RISC-V] -march=rv64g not including extension Zifencei

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104853 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #2

[Bug target/104219] [12 regression] riscv64 compiler build fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104219 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/104853] [RISC-V] -march=rv64g not including extension Zifencei

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104853 --- Comment #4 from Kito Cheng --- Thanks your info, that cause by the default ISA spec version bump issue, binutils 2.38 and GCC 11.* using different default ISA spec cause this issue, I've push a patch to GCC 11 branch [1] for this issue,

[Bug target/102957] [riscv64] ICE on bogus -march value

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102957 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/104853] [RISC-V] -march=rv64g not including extension Zifencei

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104853 Kito Cheng changed: What|Removed |Added Last reconfirmed||2022-03-30 Ever confirmed|0

[Bug target/104853] [RISC-V] -march=rv64g not including extension Zifencei

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104853 --- Comment #10 from Kito Cheng --- I plan to fix that in next few day for trunk and backport to GCC 11.

[Bug target/104219] [12 regression] riscv64 compiler build fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104219 --- Comment #5 from Kito Cheng --- I plan back port this fix to GCC 11 branch too, and will close this bug after back port.

[Bug target/104219] riscv64-elf cross compiler build fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104219 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug target/104219] riscv64-elf cross compiler build fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104219 --- Comment #3 from Kito Cheng --- Patch posted to mailing list: https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589225.html

[Bug target/104853] [RISC-V] -march=rv64g not including extension Zifencei

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104853 --- Comment #13 from Kito Cheng --- Hi rvalue: Pushed the fix to trunk and GCC 11 branch for fixing both arch-canonicalize and multilib-generator script. Tested GCC 11/trunk with --with-isa-spec=2.2/20191213. Could you try that to make sure

[Bug target/109773] RISC-V: ICE when build RVV Intrinsic in Both GCC 13 && GCC 14

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109773 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/110560] internal compiler error: in extract_constrain_insn_cached, at recog.cc:2704

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110560 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/111037] RISC-V: Invalid vsetvli fusion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111037 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/111074] RISC-V: segmentation fault during RTL pass: vsetvl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111074 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/110299] RISC-V: ICE when build RVV intrinsic widen with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110299 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug target/110277] RISC-V: ICE when build RVV intrinsic float reduction with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110277 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug target/111372] libgcc: RISCV C++ exception handling stack usage grew in 13.1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111372 --- Comment #5 from Kito Cheng --- > Ok, but it's better to have configure option or something else just > for toolchains that definitely do not use vector extension I can understand that there would be such a demand in the embedded world, but

[Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #6

[Bug c/112431] RISC-V GCC-15 feature: Support register overlap on widen RVV instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112431 --- Comment #3 from Kito Cheng --- Share some thought from my end: we've tried at least 3 different approach on LLVM side before, and now we model that as "partial early clobber", we plan to upstream this on LLVM side but just didn't get high

[Bug c/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433 --- Comment #1 from Kito Cheng --- Give few more background why LLVM must do that way: LLVM can't allocate new pseudo register during register allocation process, however spilling vector register with specific length may require scratch

[Bug target/112092] RISC-V: Wrong RVV code produced for vsetvl-11.c and vsetvlmax-8.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112092 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #4

[Bug target/111412] RISC-V:ICE in phase 6 of vsetvl pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111412 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug bootstrap/111664] [14 regression] Fails to build with mawk (error in gcc/opt-read.awk) after r14-4354-ge4a4b8e983bac8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111664 Kito Cheng changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/111600] [14 Regression] RISC-V bootstrap time regression

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111600 --- Comment #14 from Kito Cheng --- Some info for generated files: - File blankcomment code

[Bug target/111600] [14 Regression] RISC-V bootstrap time regression

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111600 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #13

[Bug tree-optimization/111791] New: RISC-V: Strange loop vectorizaion on popcount function

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111791 Bug ID: 111791 Summary: RISC-V: Strange loop vectorizaion on popcount function Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Priority: P3

[Bug target/111926] RISC-V: Use vsetvl insn replace csrr vlenb insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111926 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #1

[Bug target/111926] RISC-V: Use vsetvl insn replace csrr vlenb insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111926 --- Comment #2 from Kito Cheng --- Forgot to mention, personally I love idea to simplify code gen, I could imagine that's definitely an optimization for specific uarch :)

[Bug target/111065] [RISCV] t-linux-multilib specifies incorrect multilib reuse patterns

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111065 --- Comment #4 from Kito Cheng --- I guess I skip too much detail here, the multilib for linux isn’t really honor to the reause rule in the multilib config file for a while. That just control how multilib build, e.g. build ilp32 with which

[Bug target/111065] [RISCV] t-linux-multilib specifies incorrect multilib reuse patterns

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111065 Kito Cheng changed: What|Removed |Added Version|og13 (devel/omp/gcc-13) |14.0 CC|

[Bug target/111037] New: RISC-V: Invalid vsetvli fusion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111037 Bug ID: 111037 Summary: RISC-V: Invalid vsetvli fusion Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433 --- Comment #4 from Kito Cheng --- Yeah, 3 major goal in LLVM is improving scheduling, partial spilling and re-materialization, but none of those points are issue for RISC-V GCC :P Ref:

[Bug target/105733] riscv: Poor codegen for large stack frames

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105733 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org Ever

[Bug testsuite/106149] [13 regression] g++.dg/warn/Warray-bounds-16.C had bogus errors after r13-1366-g1eef21ccfa5988

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106149 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #2

[Bug middle-end/88345] -Os overrides -falign-functions=N on the command line

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88345 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #7

[Bug target/106338] RISC-V static-chain register may be clobbered by PLT stubs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106338 --- Comment #6 from Kito Cheng --- My understanding is static chain is sort of compiler internal implementation, any register could be picked if that is not used for passing argument, so I would also prefer keep that out psABI spec for now.

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #5 from Kito Cheng --- bset generated after change X to GPR for most zbs pattern: ``` foo: bseta1,x0,a1 andna0,a0,a1 sext.w a0,a0 ret ```

[Bug target/106585] New: RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 Bug ID: 106585 Summary: RISC-V: Mis-optimized code gen for zbs Product: gcc Version: 13.0 Status: UNCONFIRMED Keywords: missed-optimization Severity: normal

[Bug target/106532] riscv fails to build enabling ZBA/ZBB/ZBC/ZBS by default for 32bit

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106532 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #9

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #4 from Kito Cheng --- > It uses X iterator here instead of GPR, hmmm ... I think that because we have w-variant before, so use X rather than GPR here, but apparently we should revise this.

[Bug target/108185] [RISC-V]RVV assemble not set vsetvli correct.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #2

[Bug target/108185] [RISC-V] Sub-optimal code-gen for vsetvli: redundant stack store

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 Kito Cheng changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug middle-end/88345] -Os overrides -falign-functions=N on the command line

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88345 --- Comment #13 from Kito Cheng --- Patch posted before, but seems like not everybody agree: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603049.html

[Bug target/109244] internal compiler error: in setup_preferred_alternate_classes_for_new_pseudos, at ira.cc:2892

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109244 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/109244] internal compiler error: in setup_preferred_alternate_classes_for_new_pseudos, at ira.cc:2892

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109244 --- Comment #4 from Kito Cheng --- Gonna commit the fix soon, and following code is the reduced case which is reduced from your attachment. Reduced case (reduced by creduce) typedef int a; using c = float; template < typename > using e =

[Bug target/109228] warning: implicit declaration of function '__riscv_vlenb'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109228 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug c/109228] warning: implicit declaration of function '__riscv_vlenb'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109228 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #1

[Bug target/108185] [RISC-V] Sub-optimal code-gen for vsetvli: redundant stack store

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 Kito Cheng changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/108339] [11/10 only] riscv64-linux-gnu: fails to link libgcc_s.so on the GCC 10 branch

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108339 Kito Cheng changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/109479] [RISC-V] Build vint64m1_t with rv64gc_zve32x_zvl64b should promote information like "vint64m1_t requires the 'zve64x' extensions"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109479 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/109535] internal compiler error: in finalize_new_accesses, at rtl-ssa/changes.cc:471

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109535 --- Comment #5 from Kito Cheng --- Confirmed the the output is text file, it's just suffixed with .out

[Bug target/109104] [13/14 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Kito Cheng changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/109535] internal compiler error: in finalize_new_accesses, at rtl-ssa/changes.cc:471

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109535 Kito Cheng changed: What|Removed |Added Last reconfirmed||2023-04-17 Status|UNCONFIRMED

[Bug target/109535] [13/14] internal compiler error: in finalize_new_accesses, at rtl-ssa/changes.cc:471

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109535 Kito Cheng changed: What|Removed |Added Target Milestone|--- |13.2 Summary|internal compiler

[Bug target/109547] RISC-V: Multiple vsetvli for load/store loop

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109547 Kito Cheng changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

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