[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013 Li Pan changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug tree-optimization/115387] [15 regression] RISC-V: ICE in iovsprintf.c since r15-1081-ge14afbe2d1c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115387 --- Comment #2 from Li Pan --- (In reply to Edwin Lu from comment #1) > Bisected to r15-1081-ge14afbe2d1c being the first bad commit Ack, thanks Edwin, will try to reproduce this.

[Bug target/115458] [15 regression] [RISC-V] ICE in lra_split_hard_reg_for, at lra-assigns.cc:1868 unable to find a register to spill

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115458 --- Comment #2 from Li Pan --- 3700bd68d1b01f0fe6d15f8a40b7fdca0904d5aa round May 15 is OK, let me run a bisect for the first bad commit.

[Bug target/115458] [15 regression] [RISC-V] ICE in lra_split_hard_reg_for, at lra-assigns.cc:1868 unable to find a register to spill

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115458 Li Pan changed: What|Removed |Added CC||pan2.li at intel dot com --- Comment #1 from

[Bug target/115458] [15 regression] [RISC-V] ICE in lra_split_hard_reg_for, at lra-assigns.cc:1868 unable to find a register to spill

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115458 --- Comment #3 from Li Pan --- Locate the first commit 99b1daae18c095d6c94d32efb77442838e11cbfb. tree-optimization/114589 - remove profile based sink heuristics

[Bug tree-optimization/115387] [15 regression] RISC-V: ICE in iovsprintf.c since r15-1081-ge14afbe2d1c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115387 --- Comment #5 from Li Pan --- Thanks all. I can reproduce this now. Sorry I didn't run the test with glibc(only newlib), will take care of it ASAP.

[Bug tree-optimization/115387] [15 regression] RISC-V: ICE in iovsprintf.c since r15-1081-ge14afbe2d1c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115387 --- Comment #7 from Li Pan --- Thanks a lot. I am testing a fix, and will send it out after no surprise.

[Bug target/115458] [15 regression] [RISC-V] ICE in lra_split_hard_reg_for, at lra-assigns.cc:1868 unable to find a register to spill since r15-518-g99b1daae18c095

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115458 --- Comment #5 from Li Pan --- (In reply to Richard Biener from comment #4) > The bisected rev only exposes this. Thanks Richard for hint, will take a look into it.

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #1 from Li Pan --- Ack, will take care of it.

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #2 from Li Pan --- According to the ISA, Zvfhmin only contains 2 insns, quote as below " The Zvfhmin extension provides minimal support for vectors of IEEE 754-2008 binary16 values, adding conversions to and from binary32. When the

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