[Bug rtl-optimization/54540] [4.8 regression] postreload incorrectly simplifies stack adjustment into constant load into SP

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54540 --- Comment #6 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-11-20 09:35:02 UTC --- (In reply to comment #5) Can this be closed now? Well the comment 4 is still relevant, I suspect that there are still latent issues

[Bug target/55073] Wrong Neon code generation at -O2 caused by -fschedule-insns

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55073 --- Comment #1 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-11-29 17:51:49 UTC --- Author: rearnsha Date: Thu Nov 29 17:51:40 2012 New Revision: 193943 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=193943 Log: PR

[Bug target/55073] Wrong Neon code generation at -O2 caused by -fschedule-insns

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55073 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|NEW

[Bug target/55073] Wrong Neon code generation at -O2 caused by -fschedule-insns

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55073 --- Comment #4 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-11-30 09:58:38 UTC --- (In reply to comment #3) Hello Richard I updated my working copy of gcc to rev 193943, rebuilt the compiler, rebuilt the testcase I

[Bug target/55073] Wrong Neon code generation at -O2 caused by -fschedule-insns

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55073 --- Comment #8 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-11-30 14:00:21 UTC --- (In reply to comment #7) Richard, I apologize, building at -O0 (and handrolling an assembly routine to do the same computation) proves me

[Bug target/55073] Wrong Neon code generation at -O2 caused by -fschedule-insns

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55073 --- Comment #10 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-11-30 14:40:07 UTC --- (In reply to comment #9) Do you think rebuilding arm-linux-androideabi-gcc on Linux to check if the generated code is the same is worth

[Bug target/55073] Wrong Neon code generation at -O2 caused by -fschedule-insns

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55073 --- Comment #11 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-11-30 14:55:25 UTC --- Something else to check is that you are using the version of arm_neon.h that comes with gcc-4.8. This file has to match the version of GCC

[Bug target/55073] Wrong Neon code generation at -O2 caused by -fschedule-insns

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55073 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|RESOLVED

[Bug target/55073] Wrong Neon code generation at -O2 caused by -fschedule-insns

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55073 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added CC

[Bug regression/55754] FAIL: gcc.target/arm/unsigned-extend-2.c scan-assembler ands

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55754 --- Comment #3 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-12-20 15:44:23 UTC --- (In reply to comment #1) This hunk needs to be reverted. op0 is modified but it is set to an equivalent value. Perhaps you could update

[Bug rtl-optimization/55757] Suboptimal interrupt prologue/epilogue for ARMv7-M (Cortex-M3)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55757 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Priority|P3 |P5

[Bug c/56024] ARM NEON polynomial types behave as if signed

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56024 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Target||arm

[Bug c++/56025] ARM NEON polynomial types have broken overload resolution

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56025 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Target||arm

[Bug rtl-optimization/54300] [4.7 Regression] Erroneous optimization causes wrong Neon data management

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54300 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Component|target |rtl

[Bug rtl-optimization/55747] Extra registers are saved in functions that only call noreturn functions

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55747 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|NEW |RESOLVED

[Bug target/58621] With -fsection-anchors, a superfluous 'add' is performed

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58621 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug target/58621] With -fsection-anchors, a superfluous 'add' is performed

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58621 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug libgcc/55743] limits.h included unnecessarily in libgcc2.c - can break --without-headers bootstrap

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55743 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug middle-end/55653] Unnecessary initialization of vector register

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55653 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug middle-end/55653] Unnecessary initialization of vector register

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55653 --- Comment #3 from Richard Earnshaw rearnsha at gcc dot gnu.org --- On the secondary issue of initializing FP vectors to zero, we now generate for typedef double f __attribute__((vector_size(16))); f g() { f a = {0.0, 0.0}; return a; } g

[Bug target/56313] aarch64 backend not using fmls instruction

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56313 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug libgcc/58660] ARM/Thumb non-interworking code broken in libgcc

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58660 --- Comment #1 from Richard Earnshaw rearnsha at gcc dot gnu.org --- Please post patches to gcc-patc...@gcc.gnu.org and x-ref this PR.

[Bug rtl-optimization/54300] [4.7, 4.8, 4.9 Regression] regcprop incorrectly looks through parallel register swap operation

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54300 --- Comment #11 from Richard Earnshaw rearnsha at gcc dot gnu.org --- (In reply to Eric Botcazou from comment #10) and regcprop substitues d19 for d18 in insn 27, missing the fact that insn 73 is swapping the two values (thus clobbering

[Bug rtl-optimization/58668] [4.8, 4.9 regression][arm]: internal compiler error: in cond_exec_process_insns, at ifcvt.c:339

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58668 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Component|target |rtl

[Bug target/58869] switch -mcu=cortex-a7 conflicts with -march=armv7-a switch

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58869 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug bootstrap/59206] [4.9 regression] many bootstrap comparison failures on armv5tel-linux-gnueabi

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59206 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |WAITING

[Bug rtl-optimization/54300] [4.7, 4.8, 4.9 Regression] regcprop incorrectly looks through parallel register swap operation

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54300 --- Comment #13 from Richard Earnshaw rearnsha at gcc dot gnu.org --- Author: rearnsha Date: Wed Nov 20 13:55:04 2013 New Revision: 205117 URL: http://gcc.gnu.org/viewcvs?rev=205117root=gccview=rev Log: PR rtl-optimization/54300 gcc/ PR rtl

[Bug target/59216] [4.9 Regression] ARM negdi*extendsidi regression

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59216 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Last

[Bug target/59216] [4.9 Regression] ARM negdi*extendsidi regression

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59216 --- Comment #4 from Richard Earnshaw rearnsha at gcc dot gnu.org --- Author: rearnsha Date: Fri Nov 22 15:43:11 2013 New Revision: 205271 URL: http://gcc.gnu.org/viewcvs?rev=205271root=gccview=rev Log: PR target/59216 gcc/ * arm.md

[Bug target/59216] [4.9 Regression] ARM negdi*extendsidi regression

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59216 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|NEW |RESOLVED

[Bug target/59290] [4.9 regression][ARM] regression on negdi-2.c (big-endian)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59290 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Last

[Bug target/59290] [4.9 regression][ARM] regression on negdi-2.c (big-endian)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59290 --- Comment #2 from Richard Earnshaw rearnsha at gcc dot gnu.org --- The tests do need fixing for big-endian, though, since the rsb operation should write r1 in big-endian and r0 in little-endian.

[Bug c/59420] arm: broken code generated (memset from newlib 2.0)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59420 --- Comment #2 from Richard Earnshaw rearnsha at gcc dot gnu.org --- You'll get more attention paid to this if you can describe why you think the code generated is incorrect.

[Bug rtl-optimization/54300] [4.7, 4.8 Regression] regcprop incorrectly looks through parallel register swap operation

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54300 --- Comment #15 from Richard Earnshaw rearnsha at gcc dot gnu.org --- Author: rearnsha Date: Mon Dec 9 14:54:00 2013 New Revision: 205807 URL: http://gcc.gnu.org/viewcvs?rev=205807root=gccview=rev Log: PR rtl-optimization/54300 gcc/ PR

[Bug c/59448] Code generation doesn't respect C11 address-dependency

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59448 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Target||arm

[Bug rtl-optimization/59535] New: [4.9 regression] -Os code size regressions for Thumb1/Thumb2 (with LRA)?

Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org CC: ramana.radhakrishnan at arm dot com, vmakarov at redhat dot com, yvan.roux at linaro dot org

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 (with LRA)?

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #1 from Richard Earnshaw rearnsha at gcc dot gnu.org --- CSiBE code size results for Thumb2 2013/12/09 2543786 2013/12/11 2563522

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 (with LRA)?

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #2 from Richard Earnshaw rearnsha at gcc dot gnu.org --- CSiBE code size results for Thumb1 2013/12/09 2634640 2013/12/11 2683980 =1.8% size regression.

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Summary|[4.9 regression] -Os code |[4.9

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #4 from Richard Earnshaw rearnsha at gcc dot gnu.org --- Created attachment 31455 -- http://gcc.gnu.org/bugzilla/attachment.cgi?id=31455action=edit testcase Compile with -Os -mthumb -mcpu=arm7tdmi -fno-short-enums and either -mlra

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #5 from Richard Earnshaw rearnsha at gcc dot gnu.org --- Number of register-register move operations in the testcase lra:208 no-lra: 105

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #6 from Richard Earnshaw rearnsha at gcc dot gnu.org --- Created attachment 31457 -- http://gcc.gnu.org/bugzilla/attachment.cgi?id=31457action=edit Another testcase Another testcase, but this one has some obvious examples of poor

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #13 from Richard Earnshaw rearnsha at gcc dot gnu.org --- The original reason we took most high registers out of the available registers list for -Os is because saving them (they're mostly callee-saved) is quite expensive -- they have

[Bug target/59593] [arm big-endian] using ldrh access a immediate which stored in a memory by word

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59593 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Last

[Bug rtl-optimization/59535] [4.9 regression] -Os code size regressions for Thumb1/Thumb2 with LRA

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 --- Comment #15 from Richard Earnshaw rearnsha at gcc dot gnu.org --- Another testcase where the thumb1 code is poor is gcc.c-torture/execute/pr28982b.c With LRA we often get sequences such as: mov r3, sp ldr r2, .L8+16

[Bug target/59609] [4.9 Regression] LRA generates bad code for libgcc function udivmoddi4 on thumb1 target

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59609 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added CC||vmakarov

[Bug tree-optimization/54295] New: [4.7 regression] Widening multiply-accumulate operation uses wrong value extension

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54295 Bug #: 54295 Summary: [4.7 regression] Widening multiply-accumulate operation uses wrong value extension Classification: Unclassified Product: gcc Version: 4.7.0

[Bug tree-optimization/54295] [4.7 regression] Widening multiply-accumulate operation uses wrong value extension

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54295 --- Comment #1 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-08-17 12:47:35 UTC --- Created attachment 28042 -- http://gcc.gnu.org/bugzilla/attachment.cgi?id=28042 Testcase

[Bug tree-optimization/54295] [4.7 regression] Widening multiply-accumulate operation uses wrong value extension

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54295 --- Comment #2 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-08-17 12:50:32 UTC --- Testing a fix

[Bug tree-optimization/54295] [4.7/4.8 regression] Widening multiply-accumulate operation uses wrong value extension

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54295 --- Comment #3 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-08-20 12:49:55 UTC --- Author: rearnsha Date: Mon Aug 20 12:49:47 2012 New Revision: 190533 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=190533 Log: PR tree-ssa

[Bug tree-optimization/54295] [4.7/4.8 regression] Widening multiply-accumulate operation uses wrong value extension

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54295 --- Comment #4 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-08-20 14:13:40 UTC --- Author: rearnsha Date: Mon Aug 20 14:13:16 2012 New Revision: 190534 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=190534 Log: PR tree-ssa

[Bug tree-optimization/54295] [4.7 Regression] Widening multiply-accumulate operation uses wrong value extension

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54295 --- Comment #6 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-09-07 10:37:12 UTC --- Author: rearnsha Date: Fri Sep 7 10:37:08 2012 New Revision: 191066 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=191066 Log: PR tree-ssa

[Bug target/54516] [4.8 regression] ICE in reload_cse_simplify_operands, at postreload.c:403 with -O1 -march=armv7-a -mthumb

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54516 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Keywords||ice

[Bug target/54516] [4.8 regression] ICE in reload_cse_simplify_operands, at postreload.c:403 with -O1 -march=armv7-a -mthumb

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54516 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Version|4.7.2 |4.8.0

[Bug rtl-optimization/54540] New: [4.8 regression] postreload incorrectly simplifies stack adjustment into constant load into SP

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54540 Bug #: 54540 Summary: [4.8 regression] postreload incorrectly simplifies stack adjustment into constant load into SP Classification: Unclassified Product: gcc Version: 4.8.0

[Bug rtl-optimization/54540] [4.8 regression] postreload incorrectly simplifies stack adjustment into constant load into SP

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54540 --- Comment #1 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-09-10 12:46:29 UTC --- Created attachment 28160 -- http://gcc.gnu.org/bugzilla/attachment.cgi?id=28160 Testcase (not reduced)

[Bug tree-optimization/54579] New: missed optimization: ASR idiom

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54579 Bug #: 54579 Summary: missed optimization: ASR idiom Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED Keywords: missed-optimization

[Bug target/54516] [4.8 regression] ICE in reload_cse_simplify_operands, at postreload.c:403 with -O1 -march=armv7-a -mthumb

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54516 --- Comment #3 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-09-14 17:10:53 UTC --- Author: rearnsha Date: Fri Sep 14 17:10:45 2012 New Revision: 191307 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=191307 Log: PR target/54516

[Bug rtl-optimization/54540] [4.8 regression] postreload incorrectly simplifies stack adjustment into constant load into SP

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54540 --- Comment #3 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-09-14 17:10:53 UTC --- Author: rearnsha Date: Fri Sep 14 17:10:45 2012 New Revision: 191307 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=191307 Log: PR target/54516

[Bug target/54516] [4.8 regression] ICE in reload_cse_simplify_operands, at postreload.c:403 with -O1 -march=armv7-a -mthumb

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54516 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED

[Bug rtl-optimization/54540] [4.8 regression] postreload incorrectly simplifies stack adjustment into constant load into SP

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54540 --- Comment #4 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-09-15 09:57:34 UTC --- (In reply to comment #3) Author: rearnsha Date: Fri Sep 14 17:10:45 2012 New Revision: 191307 Has probably made the post-reload issues go latent

[Bug testsuite/54622] gcc.dg/vect test failures for arm big-endian

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54622 --- Comment #4 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-09-19 22:26:49 UTC --- The reasons for the vector problems in big-endian largely fall into two areas: 1) Neon vector elements are numbered from the LSB of the vector

[Bug debug/54731] [4.8 regression] arm-elf/arm-eabisim crosses fails in make-check due to undefined LFE references: corrupt debug_line tables

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54731 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW

[Bug target/54841] Bad optimization on stack fill before call on ARM

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54841 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Target||arm

[Bug target/54829] bad optimization: sub followed by cmp w/ zero (x86 ARM)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54829 --- Comment #5 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-10-13 16:04:55 UTC --- The result of the comparison is used in more than one instruction, so combine cannot safely rework the branch instructions that follow to ensure

[Bug target/54829] bad optimization: sub followed by cmp w/ zero (x86 ARM)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54829 --- Comment #6 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-10-13 16:18:03 UTC --- Note also that flag setting behaviour of the PPC instruction essentially is a comparison of the result against zero. On ARM the flags are set

[Bug target/54943] ARM - EABI - varargs floating point issue

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54943 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED

[Bug c/54983] ARM gcc creates invalid assembly: bad immediate value for 8-bit offset (1024)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54983 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED

[Bug target/55019] Incorrectly use live argument register to save high register in thumb1 prologue

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55019 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Target||arm

[Bug target/55108] bad compile-time evaluation of members of initialized union

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55108 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW

[Bug target/55108] bad compile-time evaluation of members of initialized union

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55108 --- Comment #3 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-10-30 14:15:43 UTC --- At armv6t2 and later we have a ubfx instruction available and that is enough to mask this bug.

[Bug target/56441] [ARM Thumb] generated asm code produces branch out of range error in gas with -O1 -mcpu=cortex-m3

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56441 --- Comment #8 from Richard Earnshaw rearnsha at gcc dot gnu.org 2013-02-26 17:01:36 UTC --- Please use an open (non-proprietory) file format for attaching files. I don't have access to RAR format.

[Bug target/56441] [ARM Thumb] generated asm code produces branch out of range error in gas with -O1 -mcpu=cortex-m3

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56441 --- Comment #9 from Richard Earnshaw rearnsha at gcc dot gnu.org 2013-02-26 17:03:10 UTC --- (In reply to comment #7) I was looking completely wrong, the arm_addsi3 is acting wrong. The add%?\\t%0, %1, %2 for =l,%0,Py is set

[Bug target/56470] [4.8 Regression] ICE output_operand: invalid shift operand

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56470 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW

[Bug target/50304] poor code for accessing certain element of arrays

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50304 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|WAITING |NEW

[Bug target/56315] ARM: Improve use of 64-bit constants in logical operations

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56315 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Target||arm

[Bug target/56470] [4.8 Regression] ICE output_operand: invalid shift operand

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56470 --- Comment #3 from Richard Earnshaw rearnsha at gcc dot gnu.org 2013-03-05 07:01:42 UTC --- Definitely a back-end bug. I'm not disputing that. My surprise is that this hasn't bitten us long before now, since the code has been this way

[Bug target/56441] [ARM Thumb] generated asm code produces branch out of range error in gas with -O1 -mcpu=cortex-m3

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56441 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|WAITING

[Bug tree-optimization/56096] Sub-optimal code generated for conditional shift

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56096 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW

[Bug target/56470] [4.8 Regression] ICE output_operand: invalid shift operand

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56470 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|NEW

[Bug target/56470] [4.7/4.8 Regression] ICE output_operand: invalid shift operand

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56470 --- Comment #7 from Richard Earnshaw rearnsha at gcc dot gnu.org 2013-03-11 11:48:45 UTC --- Author: rearnsha Date: Mon Mar 11 11:48:34 2013 New Revision: 196595 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=196595 Log: PR

[Bug target/56470] [4.7 Regression] ICE output_operand: invalid shift operand

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56470 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Summary|[4.7/4.8 Regression] ICE

[Bug target/56586] ARM vfpv3: Not using FPU (vsqrt op) for sqrt() / sqrtf()

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56586 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED

[Bug target/56470] [4.7 Regression] ICE output_operand: invalid shift operand

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56470 --- Comment #9 from Richard Earnshaw rearnsha at gcc dot gnu.org 2013-03-18 11:52:15 UTC --- Author: rearnsha Date: Mon Mar 18 11:52:08 2013 New Revision: 196780 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=196780 Log: PR

[Bug target/56470] [4.7 Regression] ICE output_operand: invalid shift operand

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56470 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED

[Bug c++/56617] c++ compiler error when trying to build SuperCollider with nova-simd extension on arm ubuntu

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56617 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED

[Bug target/57054] Compilation with -O3 passes, with -O2 fails (ARM/NEON)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57054 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Target||arm

[Bug target/57002] ARM back end has extra entries in attribute interrupt array.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57002 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Target|ARM |arm

[Bug libgcc/57256] Building for arm-elf with CFLAGS_FOR_TARGET=-mabi=aapcs-linux fails in libgcc/crtstuff.c

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57256 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug c++/57271] ARM: gcc generates insufficient alignment for memory passed as extra argument for function return large composite type

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57271 --- Comment #4 from Richard Earnshaw rearnsha at gcc dot gnu.org --- The ARM EABI only requires 8-byte alignment, as does Neon.

[Bug target/53124] Arm NEON narrowing right shift instructions impose incorrect operand bounds (intrinsic and asm)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53124 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug target/53124] Arm NEON narrowing right shift instructions impose incorrect operand bounds (intrinsic and asm)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53124 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED

[Bug target/53124] Arm NEON narrowing right shift instructions impose incorrect operand bounds (intrinsic and asm)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53124 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Resolution|FIXED |INVALID

[Bug target/53124] Arm NEON narrowing right shift instructions impose incorrect operand bounds (intrinsic and asm)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53124 --- Comment #5 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-04-27 12:25:06 UTC --- Just for the record, I've confirmed with the Assembler Guide team that there is a documentation fault in that document. It will be clarified in a future

[Bug bootstrap/53278] [4.8 regression] internal compiler error: in df_uses_record, at df-scan.c:3179 when compiling libgcc2.c __mulvdi3 on armv5tel-linux

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53278 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Last

[Bug target/53334] ICE in extract_insn, at recog.c:2131

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53334 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Last

[Bug target/53376] Unrecognizable compare insn generated by movsicc in arm backend.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53376 --- Comment #2 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-05-16 23:18:34 UTC --- (In reply to comment #0) extern int x; static long long p; static long long *h1 ; static long long *h2 ; void foo (void) { int i

[Bug target/53376] Unrecognizable compare insn generated by movsicc in arm backend.

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53376 --- Comment #4 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-05-17 12:07:23 UTC --- No, I think we need a separate function that is allowed to say don't do a comparison this way For example some comparisons might involve libcalls.

[Bug target/53440] [arm] generic thunk code fails for method which uses '...'

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53440 --- Comment #3 from Richard Earnshaw rearnsha at gcc dot gnu.org 2012-05-22 16:36:56 UTC --- (In reply to comment #2) Someone needs to implement the thunk functionality for arm. The ARM port does have MI thunk support. The question is why

[Bug target/53659] ARM: Using -mcpu=cortex-a9 option results in bad performance for Cortex-A9 processor in C-Ray phoronix benchmark

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53659 Richard Earnshaw rearnsha at gcc dot gnu.org changed: What|Removed |Added Target||arm

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