[Bug tree-optimization/47815] Tail call regression with GCC snapshot

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47815 Adam Warner changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug tree-optimization/69504] New: XMM register variable ICE with vector extensions

: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: adam at consulting dot net.nz Target Milestone: --- xmm_register_variable_ICE.c: #include #include typedef uint8_t u8x16_t __attribute__ ((vector_size (16))); int main(void) { register u8x16_t u8x16 asm

[Bug inline-asm/65436] Max number of extended asm +output operands currently limited to 15

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65436 --- Comment #6 from Adam Warner --- Sorry, I did not mean to send my previous comment. I updated the title and a hasty comment I was about to edit got added. It is unfair to dismiss my enhancement request as invalid. I correctly explained the cu

[Bug inline-asm/65436] Max number of extended asm +output operands currently limited to 15

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65436 Adam Warner changed: What|Removed |Added Summary|Max number of extended asm |Max number of extended asm

[Bug c/65436] New: Max number of extended asm +input operands currently limited to 15

: enhancement Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: adam at consulting dot net.nz <https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html> states: "The total number of input + output + goto operands is limited to 30.&quo

[Bug rtl-optimization/65247] [missed optimisation] Reading a callee-saved register writes to the stack

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65247 --- Comment #1 from Adam Warner --- CLANG bug report:

[Bug rtl-optimization/65247] New: [missed optimisation] Reading a callee-saved register writes to the stack

: enhancement Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: adam at consulting dot net.nz There is no way to inform the compiler one is reading a callee-saved register without the compiler also writing the register to the

[Bug inline-asm/64119] asm triggers local register variable data corruption

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64119 Adam Warner changed: What|Removed |Added Resolution|INVALID |FIXED --- Comment #5 from Adam Warner ---

[Bug inline-asm/64119] asm triggers local register variable data corruption

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64119 Adam Warner changed: What|Removed |Added Status|RESOLVED|UNCONFIRMED Resolution|INVALID

[Bug inline-asm/64119] New: asm triggers local register variable data corruption

Component: inline-asm Assignee: unassigned at gcc dot gnu.org Reporter: adam at consulting dot net.nz //asm triggers local register variable data corruption #include __attribute__((noinline)) void fn(int inputa, int inputb, int inputc) { register int a asm ("rax"); re

[Bug inline-asm/63282] New: [4.7 regression] ICE in redirect_jump_1

Assignee: unassigned at gcc dot gnu.org Reporter: adam at consulting dot net.nz Created attachment 33502 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=33502&action=edit ice.c:9:1: internal compiler error: in redirect_jump_1, at jump.c:1515 This may be related

[Bug c/38354] Spurious error: initializer element is not computable at load time

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=38354 --- Comment #11 from Adam Warner --- Thank you Joseph for clarifying in Comment 10 why this should be considered an enhancement request. It would be non-trivial to change the model of what GNU C considers a constant expression and code relying on

[Bug c/38354] Spurious error: initializer element is not computable at load time

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=38354 --- Comment #8 from Adam Warner --- Joseph, you're correct: 4005fa: b8 c6 05 40 00 moveax,0x4005c6 4005ff: 89 05 cf 04 20 00 movDWORD PTR [rip+0x2004cf],eax # 600ad4 400605: b8 c6 05 40 00

[Bug c/38354] Spurious error: initializer element is not computable at load time

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=38354 --- Comment #6 from Adam Warner --- Just to make sure I understand this correctly: 1. You won't confirm this bug because it violates the C standard. 2. GNU provides extensions to C when the C standard is too restrictive. In this case the initia

[Bug c/38354] Spurious error: initializer element is not computable at load time

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=38354 --- Comment #4 from Adam Warner --- Why can a compile-time array of 32-bit function pointers (compatible with the non-large code model) be compiled using g++ but not gcc? $ g++ -fpermissive computable_at_load_time.c computable_at_load_time.c:9:

[Bug target/46219] Generate indirect jump instruction on x86-64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46219 Adam Warner changed: What|Removed |Added Status|RESOLVED|REOPENED Version|4.6.0

[Bug target/62166] New: Poor code generation (x86-64)

Assignee: unassigned at gcc dot gnu.org Reporter: adam at consulting dot net.nz $ gcc-snapshot.sh --version gcc (Debian 20140814-1) 4.10.0 20140814 (experimental) [trunk revision 213954] weird_code_gen.c: #include typedef void (*f_t)(uint64_t rdi, uint64_t rsi, uint64_t rdx, uint64_t

[Bug c/51840] asm goto enhancement request

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51840 --- Comment #11 from Adam Warner --- Thank you for the fixed example! Just for the record only toy VM examples can be implemented using this technique. GCC documentation used to say that that the extended asm 30 operand limit might be lifted in

[Bug target/54445] TLS array lookup with negative constant is not combined into a single instruction

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54445 --- Comment #8 from Adam Warner 2012-09-13 09:01:44 UTC --- Awesome! Thanks Uros Bizjak and H.J. Lu for locating and fixing the bug.

[Bug target/54445] TLS array lookup with negative constant is not combined into a single instruction

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54445 --- Comment #1 from Adam Warner 2012-09-01 03:00:39 UTC --- Another example: $ cat negative_constant_not_combined_into_a_single_instruction_example_2.c #include __thread uint8_t byte_array[100]; uint64_t lookup_with_positive_constant(int64_t

[Bug target/54445] New: TLS array lookup with negative constant is not combined into a single instruction

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54445 Bug #: 54445 Summary: TLS array lookup with negative constant is not combined into a single instruction Classification: Unclassified Product: gcc Version: 4.7.1 Statu

[Bug middle-end/53623] [4.7/4.8 Regression] sign extension is effectively split into two x86-64 instructions

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53623 --- Comment #3 from Adam Warner 2012-06-10 23:32:19 UTC --- (Off topic "Note" correction) In my previous note I suggested the instruction "movsbq dh -> rdx". There is no such instruction! One cannot encode register ah/bh/ch/dh in an instruction

[Bug target/53623] New: [4.7 Regression] sign extension is effectively split into two x86-64 instructions

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53623 Bug #: 53623 Summary: [4.7 Regression] sign extension is effectively split into two x86-64 instructions Classification: Unclassified Product: gcc Version: 4.7.0 Statu

[Bug tree-optimization/53133] New: XOR AL,AL to zero lower 8 bits of EAX/RAX causes partial register stall (Intel Core 2)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53133 Bug #: 53133 Summary: XOR AL,AL to zero lower 8 bits of EAX/RAX causes partial register stall (Intel Core 2) Classification: Unclassified Product: gcc Version: 4.7.0

[Bug rtl-optimization/45434] x86 missed optimization: use high register (ah, bh, ch, dh) when available to make comparisons

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45434 --- Comment #8 from Adam Warner 2012-01-18 07:00:44 UTC --- Apologies for the noise. I had my machine constraints around the wrong way. Here is the fixed version of the code: #include uint64_t u8l(uint64_t in) { uint64_t out; asm ("movzbl

[Bug rtl-optimization/45434] x86 missed optimization: use high register (ah, bh, ch, dh) when available to make comparisons

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45434 --- Comment #7 from Adam Warner 2012-01-18 03:35:24 UTC --- It does not appear to be possible to generate inline asm that leaves GCC to choose the {ah, bh, ch, dh} register: #include uint64_t u8l(uint64_t in) { uint64_t out; asm ("movzbl %

[Bug tree-optimization/51840] asm goto incorrect code generation at -O2 and -O3

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51840 --- Comment #2 from Adam Warner 2012-01-13 02:08:34 UTC --- (In reply to comment #1) > I think the problem here is the label references are being moved which is > correct as GCC thinks the labels where the address was taken is not going to > happ

[Bug tree-optimization/51840] New: asm goto incorrect code generation at -O2 and -O3

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51840 Bug #: 51840 Summary: asm goto incorrect code generation at -O2 and -O3 Classification: Unclassified Product: gcc Version: 4.7.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/44281] [4.3/4.4/4.5/4.6 Regression] Global Register variable pessimisation

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44281 --- Comment #10 from Adam Warner 2011-03-05 02:01:04 UTC --- Jakub, Thanks for the explanation [The "weird" saving/restoring of %rdi into/from %r10 is because the RA chose to use %rdi for a temporary used in incrementing of REG7 and loading the

[Bug rtl-optimization/44281] [4.3/4.4/4.5/4.6 Regression] Global Register variable pessimisation

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44281 --- Comment #8 from Adam Warner 2011-03-04 10:51:01 UTC --- Jakub, I fail to see how your conclusion not to do this is supported by the facts. There are: (a) six global register variables (though the same effect can be observed with one global r

[Bug rtl-optimization/44281] [4.3/4.4/4.5/4.6 Regression] Global Register variable pessimisation

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44281 --- Comment #6 from Adam Warner 2011-03-04 07:22:47 UTC --- Below is a very simple test case of an ordinary input argument to a function being: (a) copied to a spare register (b) copied back from a spare register When the input argument is: (a

[Bug tree-optimization/47815] Tail call regression with GCC snapshot

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47815 --- Comment #3 from Adam Warner 2011-02-19 13:55:43 UTC --- OK I finally understand. Tail call optimisation also disappears when the noreturn attribute is added to the leaf functions when compiled with gcc-4.5. >From my perspective this is a bug

[Bug tree-optimization/47815] New: Tail call regression with GCC snapshot

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47815 Summary: Tail call regression with GCC snapshot Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Priority: P3 Component: tree-optimization AssignedT

[Bug tree-optimization/46551] Generate complex addressing mode CMP instruction in x86-64

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46551 --- Comment #1 from Adam Warner 2010-11-19 02:55:18 UTC --- $ gcc-snapshot.sh --version gcc (Debian 20101116-1) 4.6.0 20101116 (experimental) [trunk revision 166792] $ gcc-snapshot.sh -std=gnu99 -O3 complex_addressing_mode_cmp_inst_not_generated

[Bug tree-optimization/46551] New: Generate complex addressing mode CMP instruction in x86-64

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46551 Summary: Generate complex addressing mode CMP instruction in x86-64 Product: gcc Version: 4.6.0 Status: UNCONFIRMED Severity: minor Priority: P3 Component

[Bug rtl-optimization/46219] New: Generate indirect jump instruction on x86-64

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46219 Summary: Generate indirect jump instruction on x86-64 Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization Assi