https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113578
--- Comment #9 from Andrew Waterman ---
For my M1 running Ventura 13.6, NaN payloads _are_ propagated, sign bit
included. This test prints fffc0080:
int main()
{
volatile long long ll = 0x8010;
volatile double d;
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113578
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114809
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114087
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106531
--- Comment #5 from Andrew Waterman ---
Yeah, RISC-V International decided to define B = {Zba, Zbb, Zbs}: note, not
Zbc.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112478
--- Comment #2 from Andrew Waterman ---
Although I sketched the first draft of this patch, it’s Jeff Law who brought it
to fruition. He is more suited to help than I am.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112295
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111502
--- Comment #6 from Andrew Waterman ---
Ack, I misunderstood your earlier message. You're of course right that the
load/load/shift/or sequence is preferable to the load/load/store/store/load
sequence, on just about any practical
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111502
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248
--- Comment #3 from Andrew Waterman ---
Yikes. Thanks for the explanation, Jeff.
(cc Kito Cheng: at some point, we should revisit the pipeline modeling of Zb*
instructions for sifive-7. The short version is that all Zb* instructions can
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108247
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585
--- Comment #9 from Andrew Waterman ---
On Wed, Dec 7, 2022 at 7:02 PM palmer at gcc dot gnu.org via Gcc-bugs
wrote:
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585
>
> palmer at gcc dot gnu.org changed:
>
>What|Removed
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106691
--- Comment #3 from Andrew Waterman ---
Relaxation to gp happens at link time, and because of the relatively small
load/store offsets, the small-data limit is actually useful. I don't think we
should turn it off, because when we relax to gp,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106691
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106601
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106338
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106531
--- Comment #3 from Andrew Waterman ---
The lengthy-ISA-name problem will be addressed to a great extent by the
forthcoming introduction of ISA profiles. Although I agree the status quo is
ugly and overly verbose, I recommend against
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106531
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106265
--- Comment #6 from Andrew Waterman ---
To be clear, `li rx, 4096' isn't unsupported: it's a
very-much-supported idiom for `lui rx, 1`.
On Mon, Jul 11, 2022 at 11:45 PM rguenth at gcc dot gnu.org via
Gcc-bugs wrote:
>
>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831
--- Comment #8 from Andrew Waterman ---
Cool, thanks, Patrick.
On Mon, Mar 7, 2022 at 6:58 PM patrick at rivosinc dot com via
Gcc-bugs wrote:
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831
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> Patrick O'Neill changed:
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>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831
--- Comment #4 from Andrew Waterman ---
Correction: Appendix A recommends lr.w.aqrl + sc.w.rl.
https://github.com/riscv/riscv-isa-manual/blob/9ec8c0105dbf1492b57f6cafdb90a268628f476a/src/memory.tex#L1150-L1152
On Mon, Mar 7, 2022 at 3:51 PM
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831
--- Comment #3 from Andrew Waterman ---
Appendix A of the RISC-V ISA manual says that lr.w.aq + sc.w.aqrl
should suffice. I see the patch puts aqrl on both the load and store,
which, while correct, appears to be stronger than necessary.
(cc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102211
--- Comment #7 from Andrew Waterman ---
On Tue, Sep 7, 2021 at 10:55 PM wilson at gcc dot gnu.org via Gcc-bugs
wrote:
>
> The hardware may trap if
> you access a 32-bit value which is not properly NaN-boxed.
I don't think the following
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