[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775 Jakub Jelinek changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #11 from Jakub Jelinek --- Fixed.
[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775
--- Comment #10 from CVS Commits ---
The master branch has been updated by Jakub Jelinek :
https://gcc.gnu.org/g:6459e6537632bc06e04e6011ca7fb6488f0e8e7d
commit r12-7832-g6459e6537632bc06e04e6011ca7fb6488f0e8e7d
Author: Jakub Jelinek
Date: Sat Mar 26 16:21:36 2022 +0100
ecog: Return 1 from insn_invalid_p if REG_INC reg overlaps some stored reg
[PR103775]
The following testcase ICEs on aarch64-linux with -g and
assembles with a warning otherwise, because it emits
ldrb w0,[x0,16]!
instruction which sets the x0 register multiple times.
Due to disabled DCE (from -Og) we end up before REE with:
(insn 12 39 13 2 (set (reg:SI 1 x1 [orig:93 _2 ] [93])
(zero_extend:SI (mem/c:QI (pre_modify:DI (reg/f:DI 0 x0 [114])
(plus:DI (reg/f:DI 0 x0 [114])
(const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"pr103775.c":5:35 117 {*zero_extendqisi2_aarch64}
(expr_list:REG_INC (reg/f:DI 0 x0 [114])
(nil)))
(insn 13 12 14 2 (set (reg:DI 0 x0 [orig:112 _2 ] [112])
(zero_extend:DI (reg:SI 1 x1 [orig:93 _2 ] [93])))
"pr103775.c":5:16 111 {*zero_extendsidi2_aarch64}
(nil))
which is valid but not exactly efficient as x0 is dead after the
insn that auto-increments it. REE turns it into:
(insn 12 39 44 2 (set (reg:DI 0 x0)
(zero_extend:DI (mem/c:QI (pre_modify:DI (reg/f:DI 0 x0 [114])
(plus:DI (reg/f:DI 0 x0 [114])
(const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"pr103775.c":5:35 119 {*zero_extendqidi2_aarch64}
(expr_list:REG_INC (reg/f:DI 0 x0 [114])
(nil)))
(insn 44 12 14 2 (set (reg:DI 1 x1)
(reg:DI 0 x0)) "pr103775.c":5:35 -1
(nil))
which is invalid because it sets x0 multiple times, one
in SET_DEST of the PATTERN and once in PRE_MODIFY.
As perhaps other passes than REE might suffer from it, IMHO it is better
to reject this during change validation.
2022-03-26 Jakub Jelinek
PR rtl-optimization/103775
* recog.cc (check_invalid_inc_dec): New function.
(insn_invalid_p): Return 1 if REG_INC operand overlaps
any stored REGs.
* gcc.dg/pr103775.c: New test.
[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775 --- Comment #9 from Eric Botcazou --- > This untested patch seems to work. This looks sensible to me, maybe move the new code up to before the constraint check since it is always run.
[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775 --- Comment #8 from Jakub Jelinek --- Created attachment 52682 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=52682=edit gcc12-pr103775.patch This untested patch seems to work.
[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775 Jakub Jelinek changed: What|Removed |Added CC||ebotcazou at gcc dot gnu.org, ||rguenth at gcc dot gnu.org --- Comment #7 from Jakub Jelinek --- Though, maybe it shouldn't be the duty of every pass to check this and instead something like insn_invalid_p should reject those? If so, shall we worry about that just when reload_completed?
[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775
Jakub Jelinek changed:
What|Removed |Added
CC||jakub at gcc dot gnu.org
--- Comment #6 from Jakub Jelinek ---
I think this is a REE bug.
However inefficient (but we get that because of -Og and
-fno-forward-propagate),
(insn 12 39 13 2 (set (reg:SI 1 x1 [orig:93 _2 ] [93])
(zero_extend:SI (mem/c:QI (pre_modify:DI (reg/f:DI 0 x0 [114])
(plus:DI (reg/f:DI 0 x0 [114])
(const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"pr103775.c":5:35 117 {*zero_extendqisi2_aarch64}
(expr_list:REG_INC (reg/f:DI 0 x0 [114])
(nil)))
(insn 13 12 14 2 (set (reg:DI 0 x0 [orig:112 _2 ] [112])
(zero_extend:DI (reg:SI 1 x1 [orig:93 _2 ] [93]))) "pr103775.c":5:16
111 {*zero_extendsidi2_aarch64}
(nil))
is valid, but turning that into:
(insn 12 39 44 2 (set (reg:DI 0 x0)
(zero_extend:DI (mem/c:QI (pre_modify:DI (reg/f:DI 0 x0 [114])
(plus:DI (reg/f:DI 0 x0 [114])
(const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"pr103775.c":5:35 119 {*zero_extendqidi2_aarch64}
(expr_list:REG_INC (reg/f:DI 0 x0 [114])
(nil)))
(insn 44 12 14 2 (set (reg:DI 1 x1)
(reg:DI 0 x0)) "pr103775.c":5:35 -1
(nil))
is invalid, as one instruction can't set the same register multiple times.
[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775 Richard Biener changed: What|Removed |Added Priority|P3 |P1
[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775 --- Comment #5 from Richard Biener --- That change probably just made the latent issue trigger.
[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775 Alex Coplan changed: What|Removed |Added CC||acoplan at gcc dot gnu.org --- Comment #4 from Alex Coplan --- FWIW both the ICE and assembly failure started with r12-3252-gcad36f38576a6a781e3c62ab061c68f5b8dab13a: commit cad36f38576a6a781e3c62ab061c68f5b8dab13a Author: Roger Sayle Date: Tue Aug 31 11:45:07 2021 Preserve SUBREG_PROMOTED_VAR_P on (extend:HI (subreg/s:QI (reg:SI))).
[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775
Andrew Pinski changed:
What|Removed |Added
Component|target |rtl-optimization
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
Last reconfirmed||2021-12-20
Keywords|ice-on-valid-code |
CC||pinskia at gcc dot gnu.org
--- Comment #3 from Andrew Pinski ---
(insn 12 9 13 2 (set (reg:SI 93 [ _2 ])
(zero_extend:SI (mem/c:QI (plus:DI (reg/f:DI 65 ap)
(const_int 16 [0x10])) [1 u128_1+0 S1 A128])))
"/app/example.cpp":5:35 117 {*zero_extendqisi2_aarch64}
(nil))
Auto-increment then turns it into:
(insn 39 9 12 2 (set (reg/f:DI 114)
(reg/f:DI 65 ap)) "/app/example.cpp":5:35 -1
(nil))
(insn 12 39 13 2 (set (reg:SI 93 [ _2 ])
(zero_extend:SI (mem/c:QI (pre_modify:DI (reg/f:DI 114)
(plus:DI (reg/f:DI 114)
(const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"/app/example.cpp":5:35 117 {*zero_extendqisi2_aarch64}
(expr_list:REG_INC (reg/f:DI 114)
(nil)))
But this does not make sense as the result of the modify is not used
afterwards.
found pre add(17) r[115]=r[65]+20
16: r114:DI=ap:DI+0x10
REG_UNUSED r114:DI
15: r95:SI=r113:DI#0
REG_DEAD r113:DI
14: r113:DI=clrsb(r112:DI)
REG_DEAD r112:DI
13: r112:DI=zero_extend(r93:SI)
12: r93:SI=zero_extend([ap:DI+0x10])
12: r93:SI=zero_extend([ap:DI+0x10])
found mem(12) *(r[65]+16)
16: r114:DI=ap:DI+0x10
REG_UNUSED r114:DI
found post add(16) r[114]=r[65]+16
hmm before auto-increment:
(insn 16 15 17 2 (set (reg/f:DI 114)
(plus:DI (reg/f:DI 65 ap)
(const_int 16 [0x10]))) "/app/example.cpp":6:3 124
{*adddi3_aarch64}
(nil))
(insn 17 16 18 2 (set (reg/f:DI 115)
(plus:DI (reg/f:DI 65 ap)
(const_int 20 [0x14]))) "/app/example.cpp":6:3 124
{*adddi3_aarch64}
(expr_list:REG_DEAD (reg/f:DI 114)
(nil)))
114 is dead even before this.
Oh this is because at -Og we are not running DCE. I think there is some DF not
being updated before auto-increment too.
