http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57189
Bug #: 57189
Summary: [4.9 Regression] Vector register is spilled for vector
extract pattern
Classification: Unclassified
Product: gcc
Version: 4.9.0
Status: UNCONFIRMED
Keywords: ra
Severity: normal
Priority: P3
Component: rtl-optimization
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: ubiz...@gmail.com
Target: x86
Following testcase:
--cut here--
typedef int __v4si __attribute__ ((__vector_size__ (16)));
int test (__v4si __A)
{
return __builtin_ia32_vec_ext_v4si (__A, 0);
}
--cut here--
compiled with '-O2 -msse2 -march=k8" generates:
test:
movaps %xmm0, -24(%rsp)
movl -24(%rsp), %eax
ret
where 4.8 generates:
test:
movd %xmm0, -12(%rsp)
movl -12(%rsp), %eax
ret
The problem is with IRA, which spills V4SImode, where reload spills SImode
register for:
(insn 6 3 12 2 (set (reg:SI 62)
(vec_select:SI (reg/v:V4SI 61 [ __A ])
(parallel [
(const_int 0 [0])
]))) t.c:5 1618 {*vec_extractv4si_0}
This memory mismatch could lead to a partial memory stall.
