[Bug rtl-optimization/60851] [4.9 Regression] ICE: in extract_constrain_insn_cached, at recog.c:2117 with -flive-range-shrinkage -mdispatch-scheduler -march=bdver4

2015-03-24 Thread uros at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60851

--- Comment #15 from uros at gcc dot gnu.org ---
Author: uros
Date: Tue Mar 24 07:12:03 2015
New Revision: 221617

URL: https://gcc.gnu.org/viewcvs?rev=221617root=gccview=rev
Log:
PR rtl-optimization/60851
* recog.c (constrain_operands): Accept a pseudo register before reload
for LRA enabled targets.

testsuite/ChangeLog:

PR rtl-optimization/60851
* gcc.target/i386/pr60851.c: New test.


Added:
branches/gcc-4_9-branch/gcc/testsuite/gcc.target/i386/pr60851.c
Modified:
branches/gcc-4_9-branch/gcc/ChangeLog
branches/gcc-4_9-branch/gcc/recog.c
branches/gcc-4_9-branch/gcc/testsuite/ChangeLog


[Bug rtl-optimization/60851] [4.9 Regression] ICE: in extract_constrain_insn_cached, at recog.c:2117 with -flive-range-shrinkage -mdispatch-scheduler -march=bdver4

2015-03-24 Thread ubizjak at gmail dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60851

Uroš Bizjak ubizjak at gmail dot com changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED
   Assignee|unassigned at gcc dot gnu.org  |ubizjak at gmail dot com

--- Comment #16 from Uroš Bizjak ubizjak at gmail dot com ---
Fixed everywhere.

[Bug rtl-optimization/60851] [4.9 Regression] ICE: in extract_constrain_insn_cached, at recog.c:2117 with -flive-range-shrinkage -mdispatch-scheduler -march=bdver4

2015-03-23 Thread rth at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60851

--- Comment #14 from Richard Henderson rth at gcc dot gnu.org ---
(In reply to Uroš Bizjak from comment #13)
 In 4.9 branch, the check is located in three different places throughout
 constrain_operands. There was a big cleanup by Richard Sandiford in this
 area [1].

Looks good.

[Bug rtl-optimization/60851] [4.9 Regression] ICE: in extract_constrain_insn_cached, at recog.c:2117 with -flive-range-shrinkage -mdispatch-scheduler -march=bdver4

2015-03-22 Thread ubizjak at gmail dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60851

Uroš Bizjak ubizjak at gmail dot com changed:

   What|Removed |Added

 Status|ASSIGNED|NEW
 CC||rsandifo at gcc dot gnu.org
   Assignee|ubizjak at gmail dot com   |unassigned at gcc dot 
gnu.org
Summary|[4.9/5 Regression] ICE: in  |[4.9 Regression] ICE: in
   |extract_constrain_insn_cach |extract_constrain_insn_cach
   |ed, at recog.c:2117 with|ed, at recog.c:2117 with
   |-flive-range-shrinkage  |-flive-range-shrinkage
   |-mdispatch-scheduler|-mdispatch-scheduler
   |-march=bdver4   |-march=bdver4
  Known to fail|5.0 |

--- Comment #12 from Uroš Bizjak ubizjak at gmail dot com ---
On the 4.9 branch, the patched compiler still results in the ICE. It looks like
branch and mainline are substantially different in recog.c infrastructure, and
proposed simple patch is ineffective on the branch.

Unassigning, a recog infrastructure expert (CC'd) is needed here.

[Bug rtl-optimization/60851] [4.9 Regression] ICE: in extract_constrain_insn_cached, at recog.c:2117 with -flive-range-shrinkage -mdispatch-scheduler -march=bdver4

2015-03-22 Thread ubizjak at gmail dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60851

--- Comment #13 from Uroš Bizjak ubizjak at gmail dot com ---
Created attachment 35099
  -- https://gcc.gnu.org/bugzilla/attachment.cgi?id=35099action=edit
Proposed patch for 4.9 branch

In 4.9 branch, the check is located in three different places throughout
constrain_operands. There was a big cleanup by Richard Sandiford in this area
[1].

Richard, does the patch looks OK to you?

[1] https://gcc.gnu.org/ml/gcc-patches/2014-06/msg00530.html