https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88845
Peter Bergner changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
URL|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88845
--- Comment #4 from Peter Bergner ---
Author: bergner
Date: Wed Mar 6 15:36:43 2019
New Revision: 269428
URL: https://gcc.gnu.org/viewcvs?rev=269428=gcc=rev
Log:
gcc/
PR rtl-optimization/88845
* config/rs6000/rs6000.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88845
--- Comment #3 from Segher Boessenkool ---
(In reply to Peter Bergner from comment #2)
> Thinking about this, insn 14 doesn't look legal to me for ppc, since FP
> values in our FP regs are actually stored as 64-bit quantities, even for
> SFmode,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88845
--- Comment #2 from Peter Bergner ---
Thinking about this, insn 14 doesn't look legal to me for ppc, since FP values
in our FP regs are actually stored as 64-bit quantities, even for SFmode, so
copying a 32-bit SImode value over to a 64-bit wide
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88845
--- Comment #1 from Peter Bergner ---
After IRA, we have the following RTL with pseudo 124 being assigned to r9,
which does not meet the "f" constraint required by the inline asm:
(insn 6 5 7 2 (set (reg:SI 124)
(const_int 0 [0]))
