[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 --- Comment #6 from CVS Commits --- The master branch has been updated by Kito Cheng : https://gcc.gnu.org/g:40fc8e3d4f600d89e6b065d6f12db7a816269c8f commit r13-7138-g40fc8e3d4f600d89e6b065d6f12db7a816269c8f Author: Yanzhang Wang Date: Tue Apr 11 19:37:48 2023 +0800 RISC-V: Fix regression of -fzero-call-used-regs=all [PR109104] This patch registers a riscv specific function to TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will clean gpr and vector relevant registers. gcc/ChangeLog: PR target/109104 * config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl): New. * config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): New. (emit_vlmax_vsetvl): Use emit_hard_vlmax_vsetvl. * config/riscv/riscv.cc (vector_zero_call_used_regs): New. (riscv_zero_call_used_regs): New. (TARGET_ZERO_CALL_USED_REGS): New. gcc/testsuite/ChangeLog: PR target/109104 * gcc.target/riscv/zero-scratch-regs-1.c: New test. * gcc.target/riscv/zero-scratch-regs-2.c: New test. * gcc.target/riscv/zero-scratch-regs-3.c: New test. Signed-off-by: Yanzhang Wang Co-authored-by: Pan Li Co-authored-by: Ju-Zhe Zhong Co-authored-by: Kito Cheng
[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Priority|P3 |P4
[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Yanzhang, Wang changed: What|Removed |Added CC||yanzhang.wang at intel dot com --- Comment #5 from Yanzhang, Wang --- We are still working on it. Hope it can be pushed soon.
[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Kito Cheng changed: What|Removed |Added Status|NEW |ASSIGNED CC||kito at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |pan2.li at intel dot com --- Comment #4 from Kito Cheng --- Pan Li from Intel is working on fixing that
[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Martin Liška changed: What|Removed |Added Keywords|needs-bisection | Last reconfirmed||2023-03-30 Status|UNCONFIRMED |NEW Ever confirmed|0 |1 CC||marxin at gcc dot gnu.org --- Comment #3 from Martin Liška --- Started with r13-2819-gb4feb49cf308b3, it was rejected before the revision with: :1:17: sorry, unimplemented: argument ‘all’ is not supported for ‘-fzero-call-used-regs’ on this target
[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 --- Comment #2 from JuzheZhong --- (In reply to Roger Sayle from comment #1) > Not exactly my area of expertise, but adding > > if (!can_create_pseudo_p ()) > return false; > > at the start of legitimize_move on line 262 of riscv-v.cc should help. > Other solutions include clearing a vector register without requiring > a scalar register (to set the vector length) by xoring it with itself, > or possibly providing a riscv backend target hook to override the default > default_zero_call_used_regs implementation. > > If the vector length can be set to zero, that might be an alternative > to clearing call-used vector registers. We (me && kito) are trying to find the solution to fix it. Actually, xoring itself can not help since vxor.vv also needs vsetvl a5,zero Setting vector-length to be VLMAX. We don't have an instruction in RVV ISA can zero a whole vector register without vsetvl to setting VLMAX vector-length. I think maybe Kito knows how to fix it. We will definetely fix it soon in GCC 13. Thanks.
[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Roger Sayle changed: What|Removed |Added CC||roger at nextmovesoftware dot com --- Comment #1 from Roger Sayle --- Not exactly my area of expertise, but adding if (!can_create_pseudo_p ()) return false; at the start of legitimize_move on line 262 of riscv-v.cc should help. Other solutions include clearing a vector register without requiring a scalar register (to set the vector length) by xoring it with itself, or possibly providing a riscv backend target hook to override the default default_zero_call_used_regs implementation. If the vector length can be set to zero, that might be an alternative to clearing call-used vector registers.
[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104 Andrew Pinski changed: What|Removed |Added Target Milestone|--- |13.0
