[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743 JuzheZhong changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|--- |FIXED --- Comment #7 from JuzheZhong --- Fixed
[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743 --- Comment #6 from Li Pan --- Double confirmed the riscv-gnu-toolchain can be built successfully with the latest newlib.
[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743 --- Comment #5 from GCC Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:e5bbeedcf7020dfa3870d11cf2b85bc048655698 commit r14-6068-ge5bbeedcf7020dfa3870d11cf2b85bc048655698 Author: Pan Li Date: Thu Nov 30 15:08:50 2023 +0800 RISC-V: Bugfix for legitimize move when get vec mode in zve32f If we want to extract 64bit value but ELEN < 64, we use RVV vector mode with EEW = 32 to extract the highpart and lowpart. However, this approach doesn't honor DFmode when movdf pattern when ZVE32f and of course results in ICE when zve32f. This patch would like to reuse the approach with some additional handing, consider lowpart bits is meaningless for FP mode, we need one int reg as bridge here. For example: rtx tmp = gen_rtx_reg (DImode) reg:DI = reg:DF (fmv.d.x) // Move DF reg to DI ... perform the extract for high and low parts ... reg:DF = reg:DI (fmv.x.d) // Move DI reg back to DF after all done PR target/112743 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Take the exist (U *mode) and handle DFmode like DImode when EEW is 32bits for ZVE32F. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112743-2.c: New test. Signed-off-by: Pan Li
[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743 --- Comment #4 from Li Pan --- There may be another ICE for zve32f, will double-check about the details.
[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743 --- Comment #3 from GCC Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:25a51e98fdd504826a40775a5e5b9ffb336b5aa1 commit r14-5945-g25a51e98fdd504826a40775a5e5b9ffb336b5aa1 Author: Pan Li Date: Wed Nov 29 14:31:30 2023 +0800 RISC-V: Bugfix for ICE in block move when zve32f The exact_div requires the exactly multiple of the divider. Unfortunately, the condition will be broken when zve32f in some cases. For example, potential_ew is 8 BYTES_PER_RISCV_VECTOR * lmul1 is [4, 4] This patch would like to ensure the precondition of exact_div when get_vec_mode. PR target/112743 gcc/ChangeLog: * config/riscv/riscv-string.cc (expand_block_move): Add precondition check for exact_div. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112743-1.c: New test. Signed-off-by: Pan Li
[Bug target/112743] RISC-V: building FAIL with -march=rv64(or rv32)gc_zve32f_zvfh_zfh
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112743 Richard Biener changed: What|Removed |Added Component|c |target Last reconfirmed||2023-11-28 Ever confirmed|0 |1 Target||riscv Keywords||ice-on-valid-code Status|UNCONFIRMED |WAITING --- Comment #2 from Richard Biener --- No testcase.
