[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #5 from Jeffrey A. Law --- Fixed on the trunk.
[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001 --- Comment #4 from GCC Commits --- The master branch has been updated by Jeff Law : https://gcc.gnu.org/g:10cbfcd60f9e5bdbe486e1c0192e0f168d899b77 commit r14-9341-g10cbfcd60f9e5bdbe486e1c0192e0f168d899b77 Author: Jeff Law Date: Wed Mar 6 09:50:44 2024 -0700 [PR target/113001] Fix incorrect operand swapping in conditional move This bug totally fell off my radar. Sorry about that. We have some special casing the conditional move expander to simplify a conditional move when comparing a register against zero and that same register is one of the arms. Specifically a (eq (reg) (const_int 0)) where reg is also the true arm or (ne (reg) (const_int 0)) where reg is the false arm need not use the fully generalized conditional move, thus saving an instruction for those cases. In the NE case we swapped the operands, but didn't swap the condition, which led to the ICE due to an unrecognized pattern. THe backend actually has distinct patterns for those two cases. So swapping the operands is neither needed nor advisable. Regression tested on rv64gc and verified the new tests pass. Pushing to the trunk. PR target/113001 PR target/112871 gcc/ * config/riscv/riscv.cc (expand_conditional_move): Do not swap operands when the comparison operand is the same as the false arm for a NE test. gcc/testsuite * gcc.target/riscv/zicond-ice-3.c: New test. * gcc.target/riscv/zicond-ice-4.c: New test.
[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001 --- Comment #3 from Jeffrey A. Law --- *** Bug 112871 has been marked as a duplicate of this bug. ***
[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4
[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001 Andrew Pinski changed: What|Removed |Added CC||pinskia at gcc dot gnu.org Last reconfirmed||2024-02-22 Status|UNCONFIRMED |NEW Ever confirmed|0 |1 --- Comment #2 from Andrew Pinski --- Confirmed.
[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001 Richard Biener changed: What|Removed |Added Target Milestone|--- |14.0
[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001 --- Comment #1 from Patrick O'Neill --- Bisected to r14-3041-g18c453f0e63
