[Bug target/70568] [5/6/7 regression] PowerPC64: union of floating and fixed doesn't use POWER8 GPR/VSR moves

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568

Michael Meissner  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #10 from Michael Meissner  ---
Fixed in trunk (GCC 7) and the IBM Advance Toolchain branch for GCC 6.  See PR
71977 for more details.

[Bug target/70568] [5/6/7 regression] PowerPC64: union of floating and fixed doesn't use POWER8 GPR/VSR moves

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568

--- Comment #9 from Michael Meissner  ---
Author: meissner
Date: Tue Jan 10 17:44:17 2017
New Revision: 244279

URL: https://gcc.gnu.org/viewcvs?rev=244279=gcc=rev
Log:
[gcc]
2017-01-10  Michael Meissner  

Back port from trunk
2017-01-04  Michael Meissner  

PR target/71977
PR target/70568
PR target/78823
* config/rs6000/predicates.md (sf_subreg_operand): New predicate.
(altivec_register_operand): Do not return true if the operand
contains a SUBREG mixing SImode and SFmode.
(vsx_register_operand): Likewise.
(vsx_reg_sfsubreg_ok): New predicate.
(vfloat_operand): Do not return true if the operand contains a
SUBREG mixing SImode and SFmode.
(vint_operand): Likewise.
(vlogical_operand): Likewise.
(gpc_reg_operand): Likewise.
(int_reg_operand): Likewise.
* config/rs6000/rs6000-protos.h (valid_sf_si_move): Add declaration.
* config/rs6000/rs6000.c (valid_sf_si_move): New function to
determine if a MOVSI or MOVSF operation contains SUBREGs that mix
SImode and SFmode.
(rs6000_emit_move_si_sf_subreg): New helper function.
(rs6000_emit_move): Call rs6000_emit_move_si_sf_subreg to possbily
fixup SUBREGs involving SImode and SFmode.
* config/rs6000/vsx.md (SFBOOL_*): New constants that are operand
numbers for the new peephole2 optimization.
(peephole2 for SFmode unions): New peephole2 to optimize cases in
the GLIBC math library that do AND/IOR/XOR operations on single
precision floating point.
* config/rs6000/rs6000.h (TARGET_NO_SF_SUBREG): New internal
target macros to say whether we need to avoid SUBREGs mixing
SImode and SFmode.
(TARGET_ALLOW_SF_SUBREG): Likewise.
* config/rs6000/rs6000.md (UNSPEC_SF_FROM_SI): New unspecs.
(UNSPEC_SI_FROM_SF): Likewise.
(iorxor): Change spacing.
(and_ior_xor): New iterator for AND, IOR, and XOR.
(movsi_from_sf): New insns for SImode/SFmode SUBREG support.
(movdi_from_sf_zero_ext): Likewise.
(mov_hardfloat, FMOVE32 iterator): Use register_operand
instead of gpc_reg_operand.  Add SImode/SFmode SUBREG support.
(movsf_from_si): New insn for SImode/SFmode SUBREG support.
(fma4): Use gpc_reg_operand instead of register_operand.
(fms4): Likewise.
(fnma4): Likewise.
(fnms4): Likewise.
(nfma4): Likewise.
(nfms4): Likewise.

* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE_64BIT): Define macro
used by the above patch in a limited form.
* config/rs6000/vsx.md (peephole2 for SFmode unions): Use DFmode
for doing direct moves instead of DImode, since GCC 6.x does not
support DImode in Altivec registers.

[gcc/testsuite]
2017-01-10  Michael Meissner  

Back port from trunk
2017-01-04  Michael Meissner  

PR target/71977
PR target/70568
PR target/78823
* gcc.target/powerpc/pr71977-1.c: New tests to check whether on
64-bit VSX systems with direct move, whether we optimize common
code sequences in the GLIBC math library for float math functions.
* gcc.target/powerpc/pr71977-2.c: Likewise.


Added:
branches/ibm/gcc-6-branch/gcc/testsuite/gcc.target/powerpc/pr71977-1.c
  - copied unchanged from r244232,
trunk/gcc/testsuite/gcc.target/powerpc/pr71977-1.c
branches/ibm/gcc-6-branch/gcc/testsuite/gcc.target/powerpc/pr71977-2.c
  - copied unchanged from r244232,
trunk/gcc/testsuite/gcc.target/powerpc/pr71977-2.c
Modified:
branches/ibm/gcc-6-branch/gcc/ChangeLog.ibm
branches/ibm/gcc-6-branch/gcc/config/rs6000/predicates.md
branches/ibm/gcc-6-branch/gcc/config/rs6000/rs6000-protos.h
branches/ibm/gcc-6-branch/gcc/config/rs6000/rs6000.c
branches/ibm/gcc-6-branch/gcc/config/rs6000/rs6000.h
branches/ibm/gcc-6-branch/gcc/config/rs6000/rs6000.md
branches/ibm/gcc-6-branch/gcc/config/rs6000/vsx.md
branches/ibm/gcc-6-branch/gcc/testsuite/ChangeLog.ibm

[Bug target/70568] [5/6/7 regression] PowerPC64: union of floating and fixed doesn't use POWER8 GPR/VSR moves

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568

--- Comment #8 from Michael Meissner  ---
Author: meissner
Date: Thu Jan  5 00:43:53 2017
New Revision: 244084

URL: https://gcc.gnu.org/viewcvs?rev=244084=gcc=rev
Log:
[gcc]
2017-01-04  Michael Meissner  

PR target/71977
PR target/70568
PR target/78823
* config/rs6000/predicates.md (sf_subreg_operand): New predicate.
(altivec_register_operand): Do not return true if the operand
contains a SUBREG mixing SImode and SFmode.
(vsx_register_operand): Likewise.
(vsx_reg_sfsubreg_ok): New predicate.
(vfloat_operand): Do not return true if the operand contains a
SUBREG mixing SImode and SFmode.
(vint_operand): Likewise.
(vlogical_operand): Likewise.
(gpc_reg_operand): Likewise.
(int_reg_operand): Likewise.
* config/rs6000/rs6000-protos.h (valid_sf_si_move): Add
declaration.
* config/rs6000/rs6000.c (valid_sf_si_move): New function to
determine if a MOVSI or MOVSF operation contains SUBREGs that mix
SImode and SFmode.
(rs6000_emit_move_si_sf_subreg): New helper function.
(rs6000_emit_move): Call rs6000_emit_move_si_sf_subreg to possbily
fixup SUBREGs involving SImode and SFmode.
* config/rs6000/vsx.md (SFBOOL_*): New constants that are operand
numbers for the new peephole2 optimization.
(peephole2 for SFmode unions): New peephole2 to optimize cases in
the GLIBC math library that do AND/IOR/XOR operations on single
precision floating point.
* config/rs6000/rs6000.h (TARGET_NO_SF_SUBREG): New internal
target macros to say whether we need to avoid SUBREGs mixing
SImode and SFmode.
(TARGET_ALLOW_SF_SUBREG): Likewise.
* config/rs6000/rs6000.md (UNSPEC_SF_FROM_SI): New unspecs.
(UNSPEC_SI_FROM_SF): Likewise.
(iorxor): Change spacing.
(and_ior_xor): New iterator for AND, IOR, and XOR.
(movsi_from_sf): New insns for SImode/SFmode SUBREG support.
(movdi_from_sf_zero_ext): Likewise.
(mov_hardfloat, FMOVE32 iterator): Use register_operand
instead of gpc_reg_operand.  Add SImode/SFmode SUBREG support.
(movsf_from_si): New insn for SImode/SFmode SUBREG support.
(fma4): Use gpc_reg_operand instead of register_operand.
(fms4): Likewise.
(fnma4): Likewise.
(fnms4): Likewise.
(nfma4): Likewise.
(nfms4): Likewise.

[gcc/testsuite]
2017-01-04  Michael Meissner  

PR target/71977
PR target/70568
PR target/78823
* gcc.target/powerpc/pr71977-1.c: New tests to check whether on
64-bit VSX systems with direct move, whether we optimize common
code sequences in the GLIBC math library for float math functions.
* gcc.target/powerpc/pr71977-2.c: Likewise.


Added:
trunk/gcc/testsuite/gcc.target/powerpc/pr71977-1.c
trunk/gcc/testsuite/gcc.target/powerpc/pr71977-2.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/rs6000/predicates.md
trunk/gcc/config/rs6000/rs6000-protos.h
trunk/gcc/config/rs6000/rs6000.c
trunk/gcc/config/rs6000/rs6000.h
trunk/gcc/config/rs6000/rs6000.md
trunk/gcc/config/rs6000/vsx.md
trunk/gcc/testsuite/ChangeLog

[Bug target/70568] [5/6/7 regression] PowerPC64: union of floating and fixed doesn't use POWER8 GPR/VSR moves

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568

Michael Meissner  changed:

   What|Removed |Added

  Known to work||4.8.5
  Known to fail||4.9.4, 5.4.1, 6.2.1, 7.0

--- Comment #7 from Michael Meissner  ---
I noticed this bug and created PR 78823.  Since that's the same bug as this,
I'll take it.

[Bug target/70568] [5/6/7 regression] PowerPC64: union of floating and fixed doesn't use POWER8 GPR/VSR moves

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568

--- Comment #6 from Michael Meissner  ---
*** Bug 78823 has been marked as a duplicate of this bug. ***