[Bug target/80700] [7/8 Regression] ICE: Bus error (on SPE target)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80700 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4 CC||law at redhat dot com
[Bug target/80700] [7/8 Regression] ICE: Bus error (on SPE target)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80700
--- Comment #6 from Segher Boessenkool ---
LR and CTR together are a register class -- they both can be used as jump
target, in the same way. Converting LR to be a fixed register is not going
to be trivial, either.
But, where does it come from here:
(define_insn "*mov_si_e500_subreg4_2_be"
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
where rs6000_nonimmediate_operand is essentially nonimmediate_operand, so
int
nonimmediate_operand (rtx op, machine_mode mode)
{
return (general_operand (op, mode) && ! CONSTANT_P (op));
}
Things would work better if silly things were refused in the predicate already,
instead of trying to reload and letting the constraint deal with it.
[Bug target/80700] [7/8 Regression] ICE: Bus error (on SPE target)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80700 --- Comment #5 from Peter Bergner --- (In reply to Segher Boessenkool from comment #4) > (In reply to Peter Bergner from comment #3) >> (gdb) p reg_renumber[564] >> $1 = 65 > > 65 is LR. What. Heh, I was thinking the same thing. Seriously, why is LR an allocatable register and not just a fixed register?
[Bug target/80700] [7/8 Regression] ICE: Bus error (on SPE target)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80700 --- Comment #4 from Segher Boessenkool --- (In reply to Peter Bergner from comment #3) > I don't think my patch is the cause of the problem, more like it just > exposed more problems in the SPE code. After RA, we call into LRA to spill > a pseudo that did not get allocated a register: [...] > (gdb) p reg_renumber[564] > $1 = 65 65 is LR. What.
[Bug target/80700] [7/8 Regression] ICE: Bus error (on SPE target)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80700
--- Comment #3 from Peter Bergner ---
I don't think my patch is the cause of the problem, more like it just exposed
more problems in the SPE code. After RA, we call into LRA to spill a pseudo
that did not get allocated a register:
Breakpoint 5, lra (f=0x0) at
/home/bergner/gcc/gcc-fsf-mainline-pr80700/gcc/lra.c:2319
2319 lra_dump_file = f;
(gdb) prx 398
(insn 398 400 41 4 (set (reg:SI 564 [+4 ])
(subreg:SI (reg:V2SI 156 [ _2 ]) 4)) "pr80700.i":16 2072
{*mov_siv2si_e500_subreg4_2_be}
(expr_list:REG_DEAD (reg:V2SI 156 [ _2 ])
(nil)))
(gdb) p reg_renumber[564]
$1 = 65
(gdb) p reg_renumber[156]
$2 = -1
Then during LRA, insn 398 gets copied into a simple reg copy, which causes use
to SEGV (or trapped by rtl checking) because the subreg isn't there anymore:
(gdb) c
Continuing.
during RTL pass: reload
pr80700.i: In function ‘i5’:
pr80700.i:21:1: internal compiler error: RTL check: expected elt 0 type 'e' or
'u', have 'r' (rtx reg) in insn_extract, at insn-extract.c:3776
}
^
0x10cdc60b rtl_check_failed_type2(rtx_def const*, int, int, int, char const*,
int, char const*)
/home/bergner/gcc/gcc-fsf-mainline-pr80700/gcc/rtl.c:820
0x1177ce83 insn_extract(rtx_insn*)
/home/bergner/gcc/build/gcc-fsf-mainline-pr80700-rtl-debug/gcc/insn-extract.c:3776
0x10c25147 extract_insn(rtx_insn*)
/home/bergner/gcc/gcc-fsf-mainline-pr80700/gcc/recog.c:2317
0x10c246f7 extract_constrain_insn(rtx_insn*)
/home/bergner/gcc/gcc-fsf-mainline-pr80700/gcc/recog.c:2211
0x10a67653 check_rtl
/home/bergner/gcc/gcc-fsf-mainline-pr80700/gcc/lra.c:2128
0x10a68e03 lra(_IO_FILE*)
/home/bergner/gcc/gcc-fsf-mainline-pr80700/gcc/lra.c:2546
0x109dcebf do_reload
/home/bergner/gcc/gcc-fsf-mainline-pr80700/gcc/ira.c:5440
0x109dd63f execute
/home/bergner/gcc/gcc-fsf-mainline-pr80700/gcc/ira.c:5624
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See
[Bug target/80700] [7/8 Regression] ICE: Bus error (on SPE target)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80700 Martin Liška changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed||2017-08-09 CC||bergner at gcc dot gnu.org, ||marxin at gcc dot gnu.org Summary|[8 Regression] ICE: Bus |[7/8 Regression] ICE: Bus |error (on SPE target) |error (on SPE target) Ever confirmed|0 |1 --- Comment #2 from Martin Liška --- Confirmed, started with r244609.
