https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
H.J. Lu changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
--- Comment #8 from itsimbal at gcc dot gnu.org ---
Author: itsimbal
Date: Fri Feb 2 10:06:39 2018
New Revision: 257326
URL: https://gcc.gnu.org/viewcvs?rev=257326=gcc=rev
Log:
PR84066 Wrong shadow stack register size is saved for x32
x32 is a
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
--- Comment #7 from H.J. Lu ---
(In reply to igor.v.tsimbalist from comment #6)
> >
> > reg_ssp must be in word_mode, not in Pmode.
>
> reg_ssp is word_mode. It's reg_adj that is Pmode (it's increment to shadow
> stack).
OK.
> > Please show
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
--- Comment #6 from igor.v.tsimbalist at intel dot com ---
(In reply to H.J. Lu from comment #5)
> (In reply to igor.v.tsimbalist from comment #4)
> > Created attachment 43280 [details]
> > updated patch
>
> - mem = gen_rtx_MEM (Pmode,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
--- Comment #5 from H.J. Lu ---
(In reply to igor.v.tsimbalist from comment #4)
> Created attachment 43280 [details]
> updated patch
- mem = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
-
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
--- Comment #4 from igor.v.tsimbalist at intel dot com ---
Created attachment 43280
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=43280=edit
updated patch
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
H.J. Lu changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
--- Comment #2 from igor.v.tsimbalist at intel dot com ---
updated __builtin_setjmp and __builtin_longjmp to use 64bit instructions and
registers. The patch is attached.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84066
--- Comment #1 from igor.v.tsimbalist at intel dot com ---
Created attachment 43274
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=43274=edit
x32 patch
