[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 ktkachov at gcc dot gnu.org changed: What|Removed |Added Priority|P1 |P2 --- Comment #10 from

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 --- Comment #9 from ktkachov at gcc dot gnu.org --- Author: ktkachov Date: Tue Apr 24 16:58:49 2018 New Revision: 259614 URL: https://gcc.gnu.org/viewcvs?rev=259614=gcc=rev Log: [AArch64] PR target/85512: Tighten SIMD right shift immediate

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 Jakub Jelinek changed: What|Removed |Added Priority|P3 |P1

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 ktkachov at gcc dot gnu.org changed: What|Removed |Added Status|NEW |ASSIGNED

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 --- Comment #7 from Zdenek Sojka --- Created attachment 44014 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=44014=edit unreduced testcase (fully defined behavior at runtime, hopefully) $ aarch64-unknown-linux-gnu-gcc -O

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 --- Comment #6 from ktkachov at gcc dot gnu.org --- The right-shift SIMD instructions don't allow a shift of zero. The left-shifting ones do. So I'd expect *aarch64_lshr_sisd_or_int_3 needs to be adjusted as well

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 --- Comment #5 from Jakub Jelinek --- (In reply to ktkachov from comment #2) > Indeed a SSHR by zero is not valid. > One would hope that the optimisers would have eliminated the shift by zero It can't be guaranteed. The reason the

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 --- Comment #4 from Jakub Jelinek --- What other shift instructions don't allow 0 immediates?

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 Jakub Jelinek changed: What|Removed |Added CC||jakub at gcc dot gnu.org,

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 --- Comment #2 from ktkachov at gcc dot gnu.org --- Indeed a SSHR by zero is not valid. One would hope that the optimisers would have eliminated the shift by zero by this point but the constraints on the *aarch64_ashr_sisd_or_int_si3 pattern need

[Bug target/85512] [8 Regression] gcc generating non-existing sshr with immh == 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512 ktkachov at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|