[Bug target/87374] [8/9 Regression] ICE in extract_insn, at recog.c:2305
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87374 Thomas Preud'homme changed: What|Removed |Added Known to work||9.0 Known to fail|9.0 | --- Comment #7 from Thomas Preud'homme --- Done. Note that the fact that the ICE does not occur for GCC <= 7 suggests that -mslow-flash-data is not working as intended there since -mword-relocations disables relocations on MOVW/MOVT and -mslow-flash-data should disable all literal pool leaving nothing to do a relocatable load into register. These flags are just not meant to be used together.
[Bug target/87374] [8/9 Regression] ICE in extract_insn, at recog.c:2305
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87374 --- Comment #6 from Martin Liška --- Thomas: Can you please update Known to work?
[Bug target/87374] [8/9 Regression] ICE in extract_insn, at recog.c:2305
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87374 --- Comment #5 from Thomas Preud'homme --- Author: thopre01 Date: Wed Oct 31 10:05:54 2018 New Revision: 265662 URL: https://gcc.gnu.org/viewcvs?rev=265662=gcc=rev Log: Fix PR87374: ICE with -mslow-flash-data and -mword-relocations GCC ICEs under -mslow-flash-data and -mword-relocations because there is no way to load an address, both literal pools and MOVW/MOVT being forbidden. This patch gives an error message when both options are specified by the user and adds the according dg-skip-if directives for tests that use either of these options. It also explicitely set the option when in PIC mode as per documentation rather than always check for target_word_relocation together with flag_pic. 2018-10-31 Thomas Preud'homme gcc/ PR target/87374 * config/arm/arm.c (arm_option_check_internal): Disable the combined use of -mslow-flash-data and -mword-relocations. (arm_option_override): Enable -mword-relocations if -fpic or -fPIC. * config/arm/arm.md (SYMBOL_REF MOVT splitter): Stop checking for flag_pic. * doc/invoke.texi (-mword-relocations): Mention conflict with -mslow-flash-data. (-mslow-flash-data): Reciprocally. gcc/testsuite/ PR target/87374 * gcc.target/arm/movdi_movt.c: Skip if both -mslow-flash-data and -mword-relocations would be passed when compiling the test. * gcc.target/arm/movsi_movt.c: Likewise. * gcc.target/arm/pr81863.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-1.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-2.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-3.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-4.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-5.c: Likewise. * gcc.target/arm/tls-disable-literal-pool.c: Likewise. Modified: trunk/gcc/ChangeLog trunk/gcc/config/arm/arm.c trunk/gcc/config/arm/arm.md trunk/gcc/doc/invoke.texi trunk/gcc/testsuite/ChangeLog trunk/gcc/testsuite/gcc.target/arm/movdi_movt.c trunk/gcc/testsuite/gcc.target/arm/movsi_movt.c trunk/gcc/testsuite/gcc.target/arm/pr81863.c trunk/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c trunk/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c trunk/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c trunk/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c trunk/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c trunk/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
[Bug target/87374] [8/9 Regression] ICE in extract_insn, at recog.c:2305
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87374 --- Comment #4 from Thomas Preud'homme --- My approach was wrong, fundamentally -mslow-flash-data and -mword-relocations cannot both be in effect since there is then no way to load an address: - -mslow-flash-data forbids literal pools - -mword-relocations forbids MOVW/MOVT I've written a patch to make the two options conflicts. Testing it now.
[Bug target/87374] [8/9 Regression] ICE in extract_insn, at recog.c:2305
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87374 Thomas Preud'homme changed: What|Removed |Added Status|NEW |ASSIGNED --- Comment #3 from Thomas Preud'homme --- The ICE occurs because of a mismatch between the movw/movt splitter for arm_disable_literal_pool (-mslow-flash-data) and the arm_movt instruction pattern. The latter is guarded by -mword-relocations being disabled (via arm_valid_symbolic_address_p) since it requires patching a 16-bit immediate but not the former. Adding a similar check in the splitter causes relocation error at assembly time though as GCC generate symbol+offset references instead of doing the add as a separate instructions.
[Bug target/87374] [8/9 Regression] ICE in extract_insn, at recog.c:2305
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87374 Thomas Preud'homme changed: What|Removed |Added Last reconfirmed|2018-09-21 00:00:00 |2018-9-25 Assignee|unassigned at gcc dot gnu.org |thopre01 at gcc dot gnu.org --- Comment #2 from Thomas Preud'homme --- Can reproduce.
[Bug target/87374] [8/9 Regression] ICE in extract_insn, at recog.c:2305
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87374 Richard Biener changed: What|Removed |Added Target||arm Target Milestone|--- |8.3
[Bug target/87374] [8/9 Regression] ICE in extract_insn, at recog.c:2305
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87374 ktkachov at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW CC||avieira at gcc dot gnu.org, ||thopre01 at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from ktkachov at gcc dot gnu.org --- Confirmed.
