https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89213
--- Comment #6 from Segher Boessenkool ---
For 32-bit or smaller shifts you can use vspltisb always, or vspltis[hw] if
you prefer.
If generating code for ISA 2.07 (Power8) you don't have xxspltib but you do
have vsld/vsrd/vsrad/vrld, hrm. You
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89213
--- Comment #5 from Michael Meissner ---
Sure I could use XXSPLTIB all of the time if I limit the optimization to ISA
3.0 (power9). I was trying to add optimization for shift counts for 1..15 on
ISA 2.07 (power8) as well, hence using VSPLTISW
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89213
--- Comment #4 from Segher Boessenkool ---
You could just do
xxspltib xx,sh
vsrad 2,2,xx
(only the low 6 bits of the shift count are looked at, for 64-bit shifts,
in all vector insns).
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89213
--- Comment #3 from Michael Meissner ---
The vector shift sequence does not appear in Spec 2006 CPU compiled for power9.
The vector shift sequence does appear 4 times in the 602_gcc_s benchmark, and
once in the 683_imagick_s benchmark.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89213
Michael Meissner changed:
What|Removed |Added
Attachment #45611|0 |1
is obsolete|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89213
Michael Meissner changed:
What|Removed |Added
Severity|normal |enhancement
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89213
--- Comment #1 from Michael Meissner ---
Created attachment 45611
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=45611=edit
Proposed patch to fix the problem
This patch adds combiner insns to match attempted vector long long shifts by a
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89213
Michael Meissner changed:
What|Removed |Added
Status|UNCONFIRMED |ASSIGNED
Last reconfirmed|
