https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90317
Bug ID: 90317
Summary: [7/8/9/10] ICE for arm sha1h and wrong optimisations
on sha1h/c/m/p
Product: gcc
Version: 10.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: syl.nktaylor at gmail dot com
Target Milestone: ---
Target: arm-none-linux-gnueabihf | Neon intrinsics for sha1
Bug 1 (affects gcc versions 8 and above)
Description: calling vsha1h_u32 will throw an ICE; incompatible mode used for
zero_extend in the sha1h RTL pattern
testcase.c:
#include "arm_neon.h"
uint32_t foo (uint32_t val)
{
return vsha1h_u32 (val);
}
Error:
arm-none-linux-gnueabihf-gcc -mfpu=crypto-neon-fp-armv8 -O2 testcase.c
during RTL pass: combine
testcase.c: In function ‘foo’:
testcase.c:6:1: internal compiler error: in as_a, at machmode.h:353
6 | }
| ^
0x5ce064 as_a<scalar_int_mode>
/src/gcc/gcc/machmode.h:353
0x13d043b as_a<scalar_int_mode>
/src/gcc/gcc/combine.c:7403
0x13d043b expand_compound_operation
/src/gcc/gcc/combine.c:7360
0x13d7623 combine_simplify_rtx
/src/gcc/gcc/combine.c:6453
0x13d9d6a subst
/src/gcc/gcc/combine.c:5727
0x13d99e8 subst
/src/gcc/gcc/combine.c:5668
0x13dbe23 try_combine
/src/gcc/gcc/combine.c:3423
0x13e2048 combine_instructions
/src/gcc/gcc/combine.c:1306
0x13e2048 rest_of_handle_combine
/src/gcc/gcc/combine.c:15076
0x13e2048 execute
/src/gcc/gcc/combine.c:15121
---
Bug 2 (likely affects all gcc versions where sha1h/c/m/p was added, includes 7,
8, 9 and 10)
Testcase:
uint32_t foo (uint32x4_t val)
{
return vsha1h_u32 (vgetq_lane_u32 (val, 3));
}
incorrectly generates
sha1h.32 q0, q0
vmov.32 r0, d0[0]
without doing a vec select first for the specified lane (with something like
vmov.32 r3, d1[1] & vdup.32 q0, r3).
The bug happens on sha1h, sha1c, sha1m and sha1p. Their current RTL patterns
trigger incorrect combine pass optimisations.
---
I have a patch which I'll publish upstream soon.
