[Bug target/91188] strict_low_part operations do not work
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91188 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Target Milestone|10.2|10.0 Resolution|--- |FIXED --- Comment #6 from Uroš Bizjak --- Fixed in gcc-10.
[Bug target/91188] strict_low_part operations do not work
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91188 Jakub Jelinek changed: What|Removed |Added Target Milestone|10.0|10.2 --- Comment #5 from Jakub Jelinek --- GCC 10.1 has been released.
[Bug target/91188] strict_low_part operations do not work
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91188 --- Comment #4 from uros at gcc dot gnu.org --- Author: uros Date: Thu Jul 18 17:17:31 2019 New Revision: 273578 URL: https://gcc.gnu.org/viewcvs?rev=273578&root=gcc&view=rev Log: PR target/91188 * config/i386/i386.md (*addqi_1_slp): Use register_operand predicate for operand 0. Do not use (match_dup) to match operand 1 with operand 0. Add check in insn constraint that either input operand matches operand 0. Use SWI12 mode iterator to also handle HImode operands. (*and_1_slp): Ditto. (*qi_1_slp): Ditto. (*sub_1_slp): Use register_operand predicate for operand 0. Do not use (match_dup) to match operand 1 with operand 0. Add check in insn constraint that operand 1 matches operand 0. Use SWI12 mode iterator to also handle HImode operands. (*ashl3_1_slp): Ditto. (*3_1_slp): Ditto. (*3_1_slp): Ditto. testsuite/ChangeLog: PR target/91188 * gcc.target/i386/pr91188-1a.c: New test. * gcc.target/i386/pr91188-1b.c: Ditto. * gcc.target/i386/pr91188-1c.c: Ditto. * gcc.target/i386/pr91188-2a.c: Ditto. * gcc.target/i386/pr91188-2b.c: Ditto. * gcc.target/i386/pr91188-2c.c: Ditto. Added: trunk/gcc/testsuite/gcc.target/i386/pr91188-1a.c trunk/gcc/testsuite/gcc.target/i386/pr91188-1b.c trunk/gcc/testsuite/gcc.target/i386/pr91188-1c.c trunk/gcc/testsuite/gcc.target/i386/pr91188-2a.c trunk/gcc/testsuite/gcc.target/i386/pr91188-2b.c trunk/gcc/testsuite/gcc.target/i386/pr91188-2c.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/i386/i386.md trunk/gcc/testsuite/ChangeLog
[Bug target/91188] strict_low_part operations do not work
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91188
--- Comment #3 from Uroš Bizjak ---
The testcase involving HImode pattern:
--cut here--
struct S1
{
unsigned short val;
unsigned short pad1;
};
struct S1
__attribute__((noinline))
test_andw (struct S1 a, unsigned short b)
{
a.val &= b;
return a;
}
--cut here--
gcc -O2:
test_andw:
movl%edi, %eax # 2 [c=4 l=2] *movsi_internal/0
andw%si, %ax# 9 [c=4 l=3] *andhi_1_slp
ret # 23[c=0 l=1] simple_return_internal
[Bug target/91188] strict_low_part operations do not work
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91188
--- Comment #2 from Uroš Bizjak ---
The patched gcc compiles to:
test_andb:
movl%edi, %eax # 2 [c=4 l=2] *movsi_internal/0
andb%sil, %al # 9 [c=4 l=3] *andqi_1_slp
ret # 23[c=0 l=1] simple_return_internal
The patch also handles memory:
--cut here--
struct S1
{
unsigned char val;
unsigned char pad1;
unsigned short pad2;
};
unsigned char m;
struct S1
__attribute__((noinline))
test_andb (struct S1 a)
{
a.val &= m;
return a;
}
--cut here--
gcc -O2:
test_andb:
movl%edi, %eax # 2 [c=4 l=2] *movsi_internal/0
andbm(%rip), %al# 7 [c=8 l=6] *andqi_1_slp
ret # 20[c=0 l=1] simple_return_internal
and immediate operands:
--cut here--
struct S1
{
unsigned char val;
unsigned char pad1;
unsigned short pad2;
};
struct S1
__attribute__((noinline))
test_andb (struct S1 a)
{
a.val &= 0x2a;
return a;
}
--cut here--
gcc -O2:
test_andb:
movl%edi, %eax # 2 [c=4 l=2] *movsi_internal/0
andb$42, %al# 7 [c=4 l=2] *andqi_1_slp
ret # 20[c=0 l=1] simple_return_internal
[Bug target/91188] strict_low_part operations do not work
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91188
Uroš Bizjak changed:
What|Removed |Added
Target||x86
Status|UNCONFIRMED |ASSIGNED
Last reconfirmed||2019-07-17
Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com
Target Milestone|--- |10.0
Ever confirmed|0 |1
--- Comment #1 from Uroš Bizjak ---
._slp patterns should be written in this way, e.g. *and_1_slp:
(define_insn "*and_1_slp"
[(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+"))
(and:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0")
(match_operand:SWI12 2 "general_operand" "mn")))
(clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
/* FIXME: without this LRA can't reload this pattern, see PR82524. */
&& (rtx_equal_p (operands[0], operands[1])
|| rtx_equal_p (operands[0], operands[2]))"
"and{}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "")])
The above pattern handles QImode, as well as HImode.
