[Bug target/98981] gcc-10.2 for RISC-V has extraneous register moves

2021-02-18 Thread wilson at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98981 --- Comment #5 from Jim Wilson --- Neither of the two patches I mentioned in comment 1 can fix the problem by themselves, as we still have a mix of SImode and DImode operations. I looked at REE. It doesn't work because there is more than one

[Bug target/98981] gcc-10.2 for RISC-V has extraneous register moves

2021-02-17 Thread wilson at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98981 --- Comment #4 from Jim Wilson --- With this testcase extern void sub2 (void); void sub (int *i, int *j) { int k = *i + 1; *j = k; if (k == 0) sub2 (); } Compiling without the riscv_rtx_cost patch, I get lw a5,0(a0)

[Bug target/98981] gcc-10.2 for RISC-V has extraneous register moves

2021-02-05 Thread wilson at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98981 --- Comment #3 from Jim Wilson --- I suppose cost model problems could explain why combine didn't do the optimization. I didn't have a chance to look at that. I still think there is a fundmental problem with how we represent SImode operations,

[Bug target/98981] gcc-10.2 for RISC-V has extraneous register moves

2021-02-05 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98981 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #2

[Bug target/98981] gcc-10.2 for RISC-V has extraneous register moves

2021-02-05 Thread wilson at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98981 Jim Wilson changed: What|Removed |Added CC||wilson at gcc dot gnu.org --- Comment #1