[Bug rtl-optimization/123380] [15/16 Regression] ICE: in gen_rtx_SUBREG, at emit-rtl.cc:1048 with -O2 and _Float16
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123380
--- Comment #7 from GCC Commits ---
The master branch has been updated by Jeff Law :
https://gcc.gnu.org/g:1bede52d8c4ba434a8f4786f84f85922cc0c6152
commit r16-6940-g1bede52d8c4ba434a8f4786f84f85922cc0c6152
Author: Jeff Law
Date: Tue Jan 20 15:03:28 2026 -0700
[PR rtl-optimization/123380] Avoid creating bogus SUBREG in combine
In this issue we try to call gen_rtx_SUBREG with arguments that will
trigger an
assertion failure. In particular we're trying to create a paradoxical
subreg
of an HFmode object where the paradoxical is in DImode. That's obviously a
change in size. validate_subreg returns false for that case, thus
triggering
the assertion.
Like other cases in combine.cc and elsewhere we can check validate_subreg
before we call gen_rtx_SUBREG and if validate_subreg returns false, we can
return a safe value. So that's all this patch does.
Bootstrapped and regression tested on x86_64, also regression tested on
riscv{32,64}-elf. Pushing to the trunk.
PR rtl-optimization/123380
gcc/
* combine.cc (gen_lowpart_for_combine): Don't try to create a
paradoxical SUBREG if it's going to be rejected by validate_subreg.
gcc/testsuite/
* gcc.target/riscv/pr123380.c: New test.
[Bug rtl-optimization/123380] [15/16 Regression] ICE: in gen_rtx_SUBREG, at emit-rtl.cc:1048 with -O2 and _Float16
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123380
--- Comment #6 from Jeffrey A. Law ---
(insn 6 3 8 2 (set (reg/v:HF 140 [ f ])
(mem:HF (reg/f:DI 162 [ fp ]) [1 *fp_8(D)+0 S2 A16])) "j.c":8:16 138
{*movhf_softfloat}
(expr_list:REG_DEAD (reg/f:DI 162 [ fp ])
(nil)))
[ ... ]
(insn 9 8 44 2 (set (reg:DI 139 [ _15 ])
(subreg:DI (reg/v:HF 140 [ f ]) 0)) 275 {*movdi_64bit}
(nil))
[ ... ]
(insn 45 44 46 2 (set (reg:DI 161)
(ashiftrt:DI (ashift:DI (subreg:DI (mem:HF (reg/f:DI 162 [ fp ]) [1
*fp_8(D)+0 S2 A16]) 0)
(const_int 40 [0x28]))
(const_int 32 [0x20]))) 312 {ashlsi3_extend}
(expr_list:REG_DEAD (reg:DI 139 [ _15 ])
(nil)))
The problem happens when we try to combine those. We ultimately generate and
try to simplify this:
(set (reg:DI 161)
(ashiftrt:DI (ashift:DI (subreg:DI (mem:HF (reg/f:DI 162 [ fp ]) [1
*fp_8(D)+0 S2 A16]) 0)
(const_int 40 [0x28]))
(const_int 32 [0x20])))
$22 = void
[Bug rtl-optimization/123380] [15/16 Regression] ICE: in gen_rtx_SUBREG, at emit-rtl.cc:1048 with -O2 and _Float16
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123380 --- Comment #5 from Jeffrey A. Law --- So we're failing trying to build a paradoxical subreg for: (mem:HF (reg/f:DI 162 [ fp ]) [1 *fp_8(D)+0 S2 A16]) We want the paradoxical in DI. That fails the validate_subreg check as we're not in LRA and boom!
[Bug rtl-optimization/123380] [15/16 Regression] ICE: in gen_rtx_SUBREG, at emit-rtl.cc:1048 with -O2 and _Float16
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123380 --- Comment #4 from Jeffrey A. Law --- Prior comment was for a different bug. Sorry.
[Bug rtl-optimization/123380] [15/16 Regression] ICE: in gen_rtx_SUBREG, at emit-rtl.cc:1048 with -O2 and _Float16
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123380 --- Comment #3 from Jeffrey A. Law --- Things seem to go wrong as we create insn 14: ;; vect__4.9_18 = (vector(2) long int) vect__3.8_9; (insn 14 13 0 (set (reg:RVVM1DI 141 [ vect__4.9 ]) (sign_extend:RVVM1DI (subreg:RVVMF4HI (reg/v:DI 152 [ x ]) 0))) "j.c":6:8 -1 (nil)) That later gets split into: (insn 25 24 0 (set (reg:RVVM1DI 141 [ vect__4.9 ]) (if_then_else:RVVM1DI (unspec:RVVMF64BI [ (const_vector:RVVMF64BI [ (const_int 1 [0x1]) repeated x2 ]) (reg:DI 160) (const_int 1 [0x1]) repeated x3 (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (sign_extend:RVVM1DI (subreg:RVVMF4HI (reg/v:DI 152 [ x ]) 0)) (unspec:RVVM1DI [ (reg:DI 0 zero) ] UNSPEC_VUNDEF))) -1 (nil)) Then we go into a loop trying to reload the input to the sign_extend.
[Bug rtl-optimization/123380] [15/16 Regression] ICE: in gen_rtx_SUBREG, at emit-rtl.cc:1048 with -O2 and _Float16
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123380 Andrew Pinski changed: What|Removed |Added Status|UNCONFIRMED |NEW Keywords||needs-bisection Target Milestone|--- |15.3 Last reconfirmed||2026-01-03 Ever confirmed|0 |1 Known to work||14.2.0 --- Comment #2 from Andrew Pinski --- Confirmed.
