[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882 Segher Boessenkool changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #10 from Segher Boessenkool --- Fixed on trunk and 8; closing as fixed.
[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882 --- Comment #9 from Segher Boessenkool --- Author: segher Date: Tue Sep 18 16:24:58 2018 New Revision: 264401 URL: https://gcc.gnu.org/viewcvs?rev=264401=gcc=rev Log: Backport PR86882 fix to 8 PR rtl-optimization/86882 * rtlanal.c (reg_overlap_mentioned_p): Handle CLOBBER. Modified: branches/gcc-8-branch/gcc/ChangeLog branches/gcc-8-branch/gcc/rtlanal.c
[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882 --- Comment #8 from Segher Boessenkool --- Author: segher Date: Tue Sep 18 16:19:56 2018 New Revision: 264400 URL: https://gcc.gnu.org/viewcvs?rev=264400=gcc=rev Log: Handle CLOBBER in reg_overlap_mentioned_p (PR86882) Combine will put CLOBBER (with a non-void mode) anywhere in a pattern to poison it. reg_overlap_mentioned_p did not handle this. This patch fixes that. PR rtl-optimization/86882 * rtlanal.c (reg_overlap_mentioned_p): Handle CLOBBER. Modified: trunk/gcc/ChangeLog trunk/gcc/rtlanal.c
[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882 Segher Boessenkool changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned at gcc dot gnu.org |segher at gcc dot gnu.org --- Comment #7 from Segher Boessenkool --- I have a patch.
[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882
--- Comment #6 from Uroš Bizjak ---
(In reply to Segher Boessenkool from comment #5)
> So what is wrong about that? CONST_INTs are sign-extended always, so
> 0xff00 is just fine?
As said in Comment #2, it is not wrong, just suspicious.
(insn 10 9 11 3 (set (reg:SI 94 [ ])
(zero_extend:SI (reg:QI 92 [ ]))) "pr86882.c":10 140
{*zero_extendqisi2}
(nil))
(insn 11 10 13 3 (parallel [
(set (reg:SI 95 [ jd ])
(xor:SI (reg:SI 94 [ ])
(const_int 257 [0x101])))
(clobber (reg:CC 17 flags))
]) "pr86882.c":10 461 {*xorsi_1}
(expr_list:REG_DEAD (reg:SI 94 [ ])
(expr_list:REG_UNUSED (reg:CC 17 flags)
(nil
(insn 13 11 14 3 (parallel [
(set (reg:HI 97)
(xor:HI (subreg:HI (reg:SI 95 [ jd ]) 0)
(subreg:HI (reg:QI 92 [ ]) 0)))
(clobber (reg:CC 17 flags))
]) "pr86882.c":11 459 {*xorhi_1}
(expr_list:REG_DEAD (reg:SI 95 [ jd ])
(expr_list:REG_DEAD (reg:QI 92 [ ])
(expr_list:REG_UNUSED (reg:CC 17 flags)
(nil)
gets combined to:
Trying 10, 11 -> 13:
Successfully matched this instruction:
(set (reg:HI 95 [ jd ])
(and:HI (subreg:HI (reg:QI 92 [ ]) 0)
(const_int -256 [0xff00])))
Successfully matched this instruction:
(set (reg:HI 97)
(xor:HI (reg:HI 95 [ jd ])
(const_int 257 [0x101])))
The first one operates on paradoxical HImode subreg of QImode input operand
(valid bitmask 0xff), which is masked with 0xff00. The result is a value, which
has only highpart unmasked and lowpart = 0x00. Later, a couple instructions
operate in HImode, but finally we get to:
(insn 14 13 15 3 (set (reg:QI 92 [ ])
(subreg:QI (reg:HI 97) 0)) "pr86882.c":11 88 {*movqi_internal}
(nil))
which discards paradoxical highpart from the Himode operations. So, I guess the
above is OK (but I didn't check the validity of XOR and AND simplifications in
different modes).
It looks to me that the invalid RTX from comment #1 should read:
(set (reg:QI 97)
(const_int 1 [0x1]))
[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882 --- Comment #5 from Segher Boessenkool --- So what is wrong about that? CONST_INTs are sign-extended always, so 0xff00 is just fine?
[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882 --- Comment #4 from Uroš Bizjak --- (In reply to Segher Boessenkool from comment #3) > combine creates a clobber of const_int 0 to make sure a pattern will > not match. That is valid RTL, but further patterns constructed from > that are not (clobber on a rhs). > > The upper bits of a paradoxical subregs are defined in many cases, > see SUBREG_PROMOTED_VAR_P; does that apply here? It looks to me that "ZERO_EXTEND:SI (reg:QI)" is substituted with "AND:SI (reg:SI, 0xff)", and some simplification involving XOR and AND RTXes generates "AND (reg, 0xff00)".
[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882 --- Comment #3 from Segher Boessenkool --- combine creates a clobber of const_int 0 to make sure a pattern will not match. That is valid RTL, but further patterns constructed from that are not (clobber on a rhs). The upper bits of a paradoxical subregs are defined in many cases, see SUBREG_PROMOTED_VAR_P; does that apply here?
[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882
--- Comment #2 from Uroš Bizjak ---
Also suspicious combine transformation before the failure:
Trying 10, 11 -> 13:
10: r94:SI=zero_extend(r92:QI)
11: {r95:SI=r94:SI^0x101;clobber flags:CC;}
REG_DEAD r94:SI
REG_UNUSED flags:CC
13: {r97:HI=r95:SI#0^r92:QI#0;clobber flags:CC;}
REG_DEAD r95:SI
REG_DEAD r92:QI
REG_UNUSED flags:CC
Failed to match this instruction:
(parallel [
(set (reg:HI 97)
(xor:HI (and:HI (subreg:HI (reg:QI 92 [ ]) 0)
(const_int -256 [0xff00]))
(const_int 257 [0x101])))
(clobber (reg:CC 17 flags))
])
Failed to match this instruction:
(set (reg:HI 97)
(xor:HI (and:HI (subreg:HI (reg:QI 92 [ ]) 0)
(const_int -256 [0xff00]))
(const_int 257 [0x101])))
Successfully matched this instruction:
(set (reg:HI 95 [ jd ])
(and:HI (subreg:HI (reg:QI 92 [ ]) 0)
(const_int -256 [0xff00])))
Successfully matched this instruction:
(set (reg:HI 97)
(xor:HI (reg:HI 95 [ jd ])
(const_int 257 [0x101])))
allowing combination of insns 10, 11 and 13
original costs 4 + 4 + 4 = 12
replacement costs 6 + 4 = 10
deferring deletion of insn with uid = 10.
modifying insn i211: {r95:HI=r92:QI#0&0xff00;clobber flags:CC;}
REG_UNUSED flags:CC
REG_DEAD r92:QI
deferring rescan insn with uid = 11.
modifying insn i313: {r97:HI=r95:HI^0x101;clobber flags:CC;}
REG_UNUSED flags:CC
REG_DEAD r95:HI
deferring rescan insn with uid = 13.
The problematic insn:
(set (reg:HI 95 [ jd ])
(and:HI (subreg:HI (reg:QI 92 [ ]) 0)
(const_int -256 [0xff00])))
clears defined bits from the subreg and keeps undefined bits from the
paradoxical subreg.
[Bug rtl-optimization/86882] [9 Regression] ICE in reg_overlap_mentioned_p, at rtlanal.c:1873
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86882
Uroš Bizjak changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed||2018-08-08
CC||segher at gcc dot gnu.org
Target Milestone|--- |9.0
Ever confirmed|0 |1
--- Comment #1 from Uroš Bizjak ---
Confirmed, combine creates invalid RTX:
Trying 11, 13 -> 14:
11: {r95:HI=r92:QI#0&0xff00;clobber flags:CC;}
REG_UNUSED flags:CC
REG_DEAD r92:QI
13: {r97:HI=r95:HI^0x101;clobber flags:CC;}
REG_UNUSED flags:CC
REG_DEAD r95:HI
14: r92:QI=r97:HI#0
Failed to match this instruction:
(parallel [
(set (clobber:QI (const_int 0 [0]))
(const_int 1 [0x1]))
(set (reg:HI 97)
(xor:HI (and:HI (subreg:HI (reg:QI 92 [ ]) 0)
(const_int -256 [0xff00]))
(const_int 257 [0x101])))
])
Failed to match this instruction:
(parallel [
(set (clobber:QI (const_int 0 [0]))
(const_int 1 [0x1]))
(set (reg:HI 97)
(xor:HI (and:HI (subreg:HI (reg:QI 92 [ ]) 0)
(const_int -256 [0xff00]))
(const_int 257 [0x101])))
])
This part:
(set (clobber:QI (const_int 0 [0]))
(const_int 1 [0x1]))
is invalid and triggers assert in reg_overlap_mentioned_p.
