[Bug target/121412] [16 Regression] AArch64 SVE VLS vs VLA ICE building Pytorch with LTO
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121412
--- Comment #5 from ktkachov at gcc dot gnu.org ---
Comment on attachment 62057
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=62057
Second sleeffoo.i reproducer
>#pragma GCC aarch64 "arm_sve.h"
>typedef svfloat32_t a;
>typedef svfloat32x2_t b;
>a c();
>b d(a e, a f) {
> b g = svcreate2_f32(e, f);
> return g;
>}
>void h(b);
>void Sleef_hypotfx_u05sve() {
> a i;
> h(d(i, c()));
>}
This can be adjusted to be:
#pragma GCC aarch64 "arm_sve.h"
typedef svfloat32_t a;
typedef svfloat32x2_t b;
a c();
b d(a e, a f) {
b g = svcreate2_f32(e, f);
return g;
}
void h(b);
svfloat32_t Sleef_hypotfx_u05sve(int x, svfloat32_t xx) {
a i;
h(d(i, c()));
}
to make the Sleef_hypotfx_u05sve declaration match the prototype in foo.ii
[Bug target/121412] [16 Regression] AArch64 SVE VLS vs VLA ICE building Pytorch with LTO
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121412
--- Comment #4 from Richard Biener ---
(In reply to Richard Biener from comment #3)
> -msve-vector-bits is not specially handled in lto-wrapper and thus it will
> go the "default" and ferry that over to the link command.
>
> The flag should get into the function-specific target attribute but global
> vars can be affected which is likely the issue here.
/* The following does what the old LTO option code did,
union all target and a selected set of common options. */
for (i = 0; i < fdecoded_options.length (); ++i)
{
...
default:
if (!(cl_options[foption->opt_index].flags & CL_TARGET))
break;
...
/* Do what the old LTO code did - collect exactly one option
setting per OPT code, we pick the first we encounter.
??? This doesn't make too much sense, but when it doesn't
then we should complain. */
if (existing_opt == -1)
decoded_options.safe_push (*foption);
break;
that also means if you have "conflicting" -msve-vector-bits=... the first
one wins.
[Bug target/121412] [16 Regression] AArch64 SVE VLS vs VLA ICE building Pytorch with LTO
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121412 Richard Biener changed: What|Removed |Added Target Milestone|--- |16.0 Version|15.0|16.0
[Bug target/121412] [16 Regression] AArch64 SVE VLS vs VLA ICE building Pytorch with LTO
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121412 --- Comment #3 from Richard Biener --- -msve-vector-bits is not specially handled in lto-wrapper and thus it will go the "default" and ferry that over to the link command. The flag should get into the function-specific target attribute but global vars can be affected which is likely the issue here.
[Bug target/121412] [16 Regression] AArch64 SVE VLS vs VLA ICE building Pytorch with LTO
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121412 ktkachov at gcc dot gnu.org changed: What|Removed |Added Summary|AArch64 SVE VLS vs VLA ICE |[16 Regression] AArch64 SVE |building Pytorch with LTO |VLS vs VLA ICE building ||Pytorch with LTO Known to work||15.1.1 Known to fail||16.0 --- Comment #2 from ktkachov at gcc dot gnu.org --- Although I think the general question of VLS vs VLA is long-standing the ICE in this testcase appears as a GCC 16 regression.
