[Bug target/80082] [5/6/7 regression] GCC incorrectly assumes Cortex-r[578] have 64-bit single-copy atomic LDRD
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80082 Thomas Preud'homme changed: What|Removed |Added CC||thopre01 at gcc dot gnu.org Known to work||7.0 Assignee|prakhar.bahuguna at arm dot com|thopre01 at gcc dot gnu.org Known to fail||5.4.1, 6.3.1 --- Comment #8 from Thomas Preud'homme --- Updating known to work and known to fail fields.
[Bug target/80082] [5/6/7 regression] GCC incorrectly assumes Cortex-r[578] have 64-bit single-copy atomic LDRD
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80082 --- Comment #7 from Thomas Preud'homme --- Author: thopre01 Date: Wed Mar 22 11:35:15 2017 New Revision: 246365 URL: https://gcc.gnu.org/viewcvs?rev=246365=gcc=rev Log: Fix PR80082: LDRD erronously used for 64bit load on ARMv7-R 2017-03-22 Thomas Preud'hommegcc/ PR target/80082 * config/arm/arm-isa.h (isa_bit_lpae): New feature bit. (ISA_ARMv7ve): Add isa_bit_lpae to the definition. * config/arm/arm-protos.h (arm_arch7ve): Rename into ... (arm_arch_lpae): This. * config/arm/arm.c (arm_arch7ve): Rename into ... (arm_arch_lpae): This. Define it in term of isa_bit_lpae. * config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of arm_arch_lpae. gcc/testsuite/ PR target/80082 * gcc.target/arm/atomic_loaddi_10.c: New testcase. * gcc.target/arm/atomic_loaddi_11.c: Likewise. Added: trunk/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c trunk/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/arm/arm-isa.h trunk/gcc/config/arm/arm-protos.h trunk/gcc/config/arm/arm.c trunk/gcc/config/arm/arm.h trunk/gcc/testsuite/ChangeLog
[Bug target/80082] [5/6/7 regression] GCC incorrectly assumes Cortex-r[578] have 64-bit single-copy atomic LDRD
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80082 ktkachov at gcc dot gnu.org changed: What|Removed |Added Assignee|ktkachov at gcc dot gnu.org|prakhar.bahuguna at arm dot com --- Comment #6 from ktkachov at gcc dot gnu.org --- I believe Prakhar is working on a fix
[Bug target/80082] [5/6/7 regression] GCC incorrectly assumes Cortex-r[578] have 64-bit single-copy atomic LDRD
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80082 Richard Biener changed: What|Removed |Added Target Milestone|7.0 |5.5 --- Comment #5 from Richard Biener --- If backports were not yet released this would be a P1 (no known-to-work/fail specified though...)
[Bug target/80082] [5/6/7 regression] GCC incorrectly assumes Cortex-r[578] have 64-bit single-copy atomic LDRD
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80082 ktkachov at gcc dot gnu.org changed: What|Removed |Added Priority|P1 |P2 Assignee|unassigned at gcc dot gnu.org |ktkachov at gcc dot gnu.org --- Comment #4 from ktkachov at gcc dot gnu.org --- P2 as the bug appears in a released compiler
[Bug target/80082] [5/6/7 regression] GCC incorrectly assumes Cortex-r[578] have 64-bit single-copy atomic LDRD
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80082 ktkachov at gcc dot gnu.org changed: What|Removed |Added Status|NEW |ASSIGNED CC||ktkachov at gcc dot gnu.org --- Comment #3 from ktkachov at gcc dot gnu.org --- Confirmed. The problem is that these Cortex-R cores combined with the bit_adiv isa bit end up having the same feature set as armv7ve as far as GCC can tell. I think the best approach here is to create an isa_bit_lpae that's unique to armv7ve (and higher A-profile arches)
[Bug target/80082] [5/6/7 regression] GCC incorrectly assumes Cortex-r[578] have 64-bit single-copy atomic LDRD
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80082 Richard Earnshaw changed: What|Removed |Added Summary|[6/7 regression] GCC|[5/6/7 regression] GCC |incorrectly assumes |incorrectly assumes |Cortex-r[578] have 64-bit |Cortex-r[578] have 64-bit |single-copy atomic LDRD |single-copy atomic LDRD --- Comment #2 from Richard Earnshaw --- It looks as though this patch was then backported onto older releases as well, so GCC-5 also regressed.