[Bug target/88469] [7/8 regression] AAPCS/AAPCS64 - Struct with 64-bit bitfield (128-bit on AArch64) may be passed in wrong registers
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88469
Jenim changed:
What|Removed |Added
CC||jenimjohn at orgs dot com.co
--- Comment #19 from Jenim ---
003c21e0 <_ZN11cgraph_node11create_edgeEPS_P5gcall13profile_count>:
3c21e0: e24dd008sub sp, sp, #8
3c21e4: e309c130movwip, #37168 ; 0x9130
3c21e8: e340c133movtip, #307; 0x133
3c21ec: e92d4370push{r4, r5, r6, r8, r9, lr}
3c21f0: e24dd018sub sp, sp, #24
3c21f4: e1a05001mov r5, r1
3c21f8: e1a06000mov r6, r0
3c21fc: e58d3034str r3, [sp, #52] ; 0x34
3c2200: e1a03002mov r3, r2
3c2204: e1cd83d4ldrdr8, [sp, #52] ; 0x34
3c2208: e1a02001mov r2, r1
3c220c: e28d1018add r1, sp, #24
3c2210: e3a0e000mov lr, #0
3c2214: e1cd81f0strdr8, [sp, #16]
3c2218: e9110003ldmdb r1, {r0, r1}
3c221c: e58de008str lr, [sp, #8]
3c2220: e88d0003stm sp, {r0, r1}
3c2224: e1a01006mov r1, r6
3c2228: e59cldr r0, [ip]
3c222c: eb43bl 3c1f40
<_ZN12symbol_table11create_edgeEP11cgraph_nodeS1_P5gcall13profile_countb>
3c2230: e1a04000mov r4, r0
3c2234: eb071320bl 586ebc
<_Z24initialize_inline_failedP11cgraph_edge>
3c2238: e5953044ldr r3, [r5, #68] ; 0x44
3c223c: e1a4mov r0, r4
3c2240: e353cmp r3, #0
3c2244: e5843014str r3, [r4, #20]
3c2248: 15834010strne r4, [r3, #16]
3c224c: e5963040ldr r3, [r6, #64] ; 0x40
3c2250: e353cmp r3, #0
3c2254: e584301cstr r3, [r4, #28]
3c2258: 15834018strne r4, [r3, #24]
3c225c: e5864040str r4, [r6, #64] ; 0x40
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3c2260: e5854044str r4, [r5, #68] ; 0x44
3c2264: e28dd018add sp, sp, #24
3c2268: e8bd4370pop {r4, r5, r6, r8, r9, lr}
003c21e0 <_ZN11cgraph_node11create_edgeEPS_P5gcall13profile_count>:
3c21e0: e24dd008sub sp, sp, #8
3c21e4: e309c130movwip, #37168 ; 0x9130
3c21e8: e340c133movtip, #307; 0x133
3c21ec: e92d4370push{r4, r5, r6, r8, r9, lr}
3c21f0: e24dd018sub sp, sp, #24
3c21f4: e1a05001mov r5, r1
3c21f8: e1a06000mov r6, r0
3c21fc: e58d3034str r3, [sp, #52] ; 0x34
3c2200: e1a03002mov r3, r2
3c2204: e1cd83d4ldrdr8, [sp, #52] ; 0x34
3c2208: e1a02001mov r2, r1
3c220c: e28d1018add r1, sp, #24
3c2210: e3a0e000mov lr, #0
3c2214: e1cd81f0strdr8, [sp, #16]
3c2218: e9110003ldmdb r1, {r0, r1}
3c221c: e58de008str lr, [sp, #8]
3c2220: e88d0003stm sp, {r0, r1}
3c2224: e1a01006mov r1, r6
3c2228: e59cldr r0, [ip]
3c222c: eb43bl 3c1f40
<_ZN12symbol_table11create_edgeEP11cgraph_nodeS1_P5gcall13profile_countb>
3c2230: e1a04000mov r4, r0
3c2234: eb071320bl 586ebc
<_Z24initialize_inline_failedP11cgraph_edge>
3c2238: e5953044ldr r3, [r5, #68] ; 0x44
3c223c: e1a4mov r0, r4
3c2240: e353cmp r3, #0
3c2244: e5843014str r3, [r4, #20]
3c2248: 15834010strne r4, [r3, #16]
3c224c: e5963040ldr r3, [r6, #64] ; 0x40
3c2250: e353cmp r3, #0
3c2254: e584301cstr r3, [r4, #28]
3c2258: 15834018strne r4, [r3, #24]
3c225c: e5864040str r4, [r6, #64] ; 0x40
3c2260: e5854044str r4, [r5, #68] ; 0x44
3c2264: e28dd018add sp, sp, #24
3c2268: e8bd4370pop {r4, r5, r6, r8, r9, lr}
3c226c: e28dd008add sp, sp, #8
3c2270: e12fff1ebx lr
3c226c: e28dd008add sp, sp, #8
3c2270: e12fff1ebx lr
[Bug target/88469] [7/8 regression] AAPCS/AAPCS64 - Struct with 64-bit bitfield (128-bit on AArch64) may be passed in wrong registers
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88469
--- Comment #18 from Jenim ---
003c21e0 <_ZN11cgraph_node11create_edgeEPS_P5gcall13profile_count>:
3c21e0: e24dd008sub sp, sp, #8
3c21e4: e309c130movwip, #37168 ; 0x9130
3c21e8: e340c133movtip, #307; 0x133
3c21ec: e92d4370push{r4, r5, r6, r8, r9, lr}
3c21f0: e24dd018sub sp, sp, #24
3c21f4: e1a05001mov r5, r1
3c21f8: e1a06000mov r6, r0
3c21fc: e58d3034str r3, [sp, #52] ; 0x34
3c2200: e1a03002mov r3, r2
3c2204: e1cd83d4ldrdr8, [sp, #52] ; 0x34
3c2208: e1a02001mov r2, r1
3c220c: e28d1018add r1, sp, #24
3c2210: e3a0e000mov lr, #0
3c2214: e1cd81f0strdr8, [sp, #16]
3c2218: e9110003ldmdb r1, {r0, r1}
3c221c: e58de008str lr, [sp, #8]
3c2220: e88d0003stm sp, {r0, r1}
3c2224: e1a01006mov r1, r6
3c2228: e59cldr r0, [ip]
3c222c: eb43bl 3c1f40
<_ZN12symbol_table11create_edgeEP11cgraph_nodeS1_P5gcall13profile_countb>
3c2230: e1a04000mov r4, r0
3c2234: eb071320bl 586ebc
<_Z24initialize_inline_failedP11cgraph_edge>
3c2238: e5953044ldr r3, [r5, #68] ; 0x44
3c223c: e1a4mov r0, r4
3c2240: e353cmp r3, #0
3c2244: e5843014str r3, [r4, #20]
3c2248: 15834010strne r4, [r3, #16]
3c224c: e5963040ldr r3, [r6, #64] ; 0x40
3c2250: e353cmp r3, #0
3c2254: e584301cstr r3, [r4, #28]
3c2258: 15834018strne r4, [r3, #24]
3c225c: e5864040str r4, [r6, #64] ; 0x40
3c2260: e5854044str r4, [r5, #68] ; 0x44
3c2264: e28dd018add sp, sp, #24
3c2268: e8bd4370pop {r4, r5, r6, r8, r9, lr}
3c226c: e28dd008add sp, sp, #8
3c2270: e12fff1ebx lr
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003c21e0 <_ZN11cgraph_node11create_edgeEPS_P5gcall13profile_count>:
3c21e0: e24dd008sub sp, sp, #8
3c21e4: e309c130movwip, #37168 ; 0x9130
3c21e8: e340c133movtip, #307; 0x133
3c21ec: e92d4370push{r4, r5, r6, r8, r9, lr}
3c21f0: e24dd018sub sp, sp, #24
3c21f4: e1a05001mov r5, r1
3c21f8: e1a06000mov r6, r0
3c21fc: e58d3034str r3, [sp, #52] ; 0x34
3c2200: e1a03002mov r3, r2
3c2204: e1cd83d4ldrdr8, [sp, #52] ; 0x34
3c2208: e1a02001mov r2, r1
3c220c: e28d1018add r1, sp, #24
3c2210: e3a0e000mov lr, #0
3c2214: e1cd81f0strdr8, [sp, #16]
3c2218: e9110003ldmdb r1, {r0, r1}
3c221c: e58de008str lr, [sp, #8]
3c2220: e88d0003stm sp, {r0, r1}
3c2224: e1a01006mov r1, r6
3c2228: e59cldr r0, [ip]
3c222c: eb43bl 3c1f40
<_ZN12symbol_table11create_edgeEP11cgraph_nodeS1_P5gcall13profile_countb>
3c2230: e1a04000mov r4, r0
3c2234: eb071320bl 586ebc
<_Z24initialize_inline_failedP11cgraph_edge>
3c2238: e5953044ldr r3, [r5, #68] ; 0x44
3c223c: e1a4mov r0, r4
3c2240: e353cmp r3, #0
3c2244: e5843014str r3, [r4, #20]
3c2248: 15834010strne r4, [r3, #16]
3c224c: e5963040ldr r3, [r6, #64] ; 0x40
3c2250: e353cmp r3, #0
3c2254: e584301cstr r3, [r4, #28]
3c2258: 15834018strne r4, [r3, #24]
3c225c: e5864040str r4, [r6, #64] ; 0x40
3c2260: e5854044str r4, [r5, #68] ; 0x44
3c2264: e28dd018add sp, sp, #24
3c2268: e8bd4370pop {r4, r5, r6, r8, r9, lr}
3c226c: e28dd008add sp, sp, #8
3c2270: e12fff1ebx lr
[Bug target/88469] [7/8 regression] AAPCS/AAPCS64 - Struct with 64-bit bitfield (128-bit on AArch64) may be passed in wrong registers
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88469 Jenim changed: What|Removed |Added CC||jenimjohn at orgs dot com.co --- Comment #17 from Jenim --- if you have root access on your board you can modify the kernel's behaviour for various unaligned accesses by changing /proc/cpu/alignment https://aodongluc.vn/ https://masaimaraafrica.com/ https://serengetisafaritour.com/ https://bestcoinlist.io/
[Bug target/88469] [7/8 regression] AAPCS/AAPCS64 - Struct with 64-bit bitfield (128-bit on AArch64) may be passed in wrong registers
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88469 Stefan Ring changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #16 from Stefan Ring --- This was already fixed by the commits in comments #8-#11.
[Bug target/88469] [7/8 regression] AAPCS/AAPCS64 - Struct with 64-bit bitfield (128-bit on AArch64) may be passed in wrong registers
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88469 Richard Biener changed: What|Removed |Added Target Milestone|7.5 |8.4 --- Comment #15 from Richard Biener --- The GCC 7 branch is being closed, re-targeting to GCC 8.4.
[Bug target/88469] [7/8 regression] AAPCS/AAPCS64 - Struct with 64-bit bitfield (128-bit on AArch64) may be passed in wrong registers
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88469 --- Comment #14 from Stefan Ring --- (In reply to Richard Earnshaw from comment #13) > Note that if you have root access on your board you can modify the kernel's > behaviour for various unaligned accesses by changing /proc/cpu/alignment > (see Documentation/arm/mem_alignment in the kernel sources). You might want > to try setting this to 3 to get the kernel to report (but fix up) any > misaligned accesses). I know that, but armv7 does not trap at all for misaligned ldrd, at the hardware level. It does trap if it’s not even 32bit-aligned, but that’s a different matter.
[Bug target/88469] [7/8 regression] AAPCS/AAPCS64 - Struct with 64-bit bitfield (128-bit on AArch64) may be passed in wrong registers
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88469 --- Comment #13 from Richard Earnshaw --- (In reply to Stefan Ring from comment #12) > Unfortunately my armv5 device has died in the meantime, so I cannot verify > my original use case. The behavior is indeed different on armv7. It does not > trap, even for the original misaligned code. And contrary to x86, where the > alignment check flag can be changed by user space, this is a privileged > operation on arm, so I cannot even selectively enable it. Note that if you have root access on your board you can modify the kernel's behaviour for various unaligned accesses by changing /proc/cpu/alignment (see Documentation/arm/mem_alignment in the kernel sources). You might want to try setting this to 3 to get the kernel to report (but fix up) any misaligned accesses).
[Bug target/88469] [7/8 regression] AAPCS/AAPCS64 - Struct with 64-bit bitfield (128-bit on AArch64) may be passed in wrong registers
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88469 --- Comment #12 from Stefan Ring --- Unfortunately my armv5 device has died in the meantime, so I cannot verify my original use case. The behavior is indeed different on armv7. It does not trap, even for the original misaligned code. And contrary to x86, where the alignment check flag can be changed by user space, this is a privileged operation on arm, so I cannot even selectively enable it.
[Bug target/88469] [7/8 regression] AAPCS/AAPCS64 - Struct with 64-bit bitfield (128-bit on AArch64) may be passed in wrong registers
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88469 --- Comment #11 from Richard Earnshaw --- Author: rearnsha Date: Fri Jan 25 17:09:33 2019 New Revision: 268273 URL: https://gcc.gnu.org/viewcvs?rev=268273=gcc=rev Log: This is pretty unlikely in real code, but similar to Arm, the AArch64 ABI has a bug with the handling of 128-bit bit-fields, where if the bit-field dominates the overall alignment the back-end code may end up passing the argument correctly. This is a regression that started in gcc-6 when the ABI support code was updated to support overaligned types. The fix is very similar in concept to the Arm fix. 128-bit bit-fields are fortunately extremely rare, so I'd be very surprised if anyone has been bitten by this. PR target/88469 gcc/ * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add new argument ABI_BREAK. Set to true if the calculated alignment has changed in gcc-9. Check bit-fields for their base type alignment. (aarch64_layout_arg): Warn if argument passing has changed in gcc-9. (aarch64_function_arg_boundary): Likewise. (aarch64_gimplify_va_arg_expr): Likewise. gcc/testsuite/ * gcc.target/aarch64/aapcs64/test_align-10.c: New test. * gcc.target/aarch64/aapcs64/test_align-11.c: New test. * gcc.target/aarch64/aapcs64/test_align-12.c: New test. Added: trunk/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-10.c trunk/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-11.c trunk/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-12.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/aarch64/aarch64.c trunk/gcc/testsuite/ChangeLog
