[gcc r15-1587] [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

https://gcc.gnu.org/g:a424318d32103dde827e8507fa27d24d33407ec9 commit r15-1587-ga424318d32103dde827e8507fa27d24d33407ec9 Author: Sergei Lewis Date: Mon Jun 24 14:20:14 2024 -0600 [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension This is primarily Sergei's work, my

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move()

https://gcc.gnu.org/g:f3fecf54f0a91e8a9b65e1ce6b984324654b2e2d commit f3fecf54f0a91e8a9b65e1ce6b984324654b2e2d Author: Artemiy Volkov Date: Sun Jun 23 14:54:00 2024 -0600 [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move() Presently, the code fragment:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extracting INTVAL

https://gcc.gnu.org/g:378cecaed950d1a09ce6b3540f582735ba3e1a89 commit 378cecaed950d1a09ce6b3540f582735ba3e1a89 Author: Jeff Law Date: Sun Jun 23 08:26:25 2024 -0600 [committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extracting INTVAL Run-of-the-mill checking

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests

https://gcc.gnu.org/g:43fd6784e05e28789f53a0ed100cf30d21daa5cc commit 43fd6784e05e28789f53a0ed100cf30d21daa5cc Author: Craig Blackmore Date: Sat Jun 22 22:07:06 2024 -0600 [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests These tests check the sched2 dump, so skip them for

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2] RISC-V: Remove integer vector eqne pattern

https://gcc.gnu.org/g:6d2cbb47ad006038785d56853b1b4c3e83d83b55 commit 6d2cbb47ad006038785d56853b1b4c3e83d83b55 Author: demin.han Date: Sat Jun 22 22:02:02 2024 -0600 [PATCH v2] RISC-V: Remove integer vector eqne pattern We can unify eqne and other comparison operations.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well

https://gcc.gnu.org/g:83ba88a7cba51177fd9f512a78a93f423ab9f0f5 commit 83ba88a7cba51177fd9f512a78a93f423ab9f0f5 Author: Jeff Law Date: Sat Jun 22 10:39:51 2024 -0600 [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well > the test should probably also be skipped on -Oz: >

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Minor cleanup/improvement to bset/binv patterns

https://gcc.gnu.org/g:23e7e8c94fe6a0385d15503d878bfb75c718eb14 commit 23e7e8c94fe6a0385d15503d878bfb75c718eb14 Author: Jeff Law Date: Thu Jun 20 08:43:37 2024 -0600 [RISC-V] Minor cleanup/improvement to bset/binv patterns Changes since V1: Whitespace fixes noted by the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2] RISC-V: Remove float vector eqne pattern

https://gcc.gnu.org/g:eeead7eee12c4d3bc78c07fe6061c6d922a2dcbc commit eeead7eee12c4d3bc78c07fe6061c6d922a2dcbc Author: demin.han Date: Wed Jun 19 16:21:13 2024 -0600 [PATCH v2] RISC-V: Remove float vector eqne pattern We can unify eqne and other comparison operations.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils

https://gcc.gnu.org/g:3eb4898422071a21d72d5ad388b5b5f2af68efe8 commit 3eb4898422071a21d72d5ad388b5b5f2af68efe8 Author: Patrick O'Neill Date: Tue Jun 18 14:40:15 2024 -0700 RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils Binutils 2.42 and before don't support

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 9

https://gcc.gnu.org/g:aea32d1c19aaed2b1b80102c6621c33729cd615e commit aea32d1c19aaed2b1b80102c6621c33729cd615e Author: Pan Li Date: Wed Jun 19 21:02:27 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 9 After the middle-end support the form 9 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 10

https://gcc.gnu.org/g:19bab664d3be18130e0889ce86def9e923e5fa23 commit 19bab664d3be18130e0889ce86def9e923e5fa23 Author: Pan Li Date: Wed Jun 19 21:14:31 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 10 After the middle-end support the form 10 of unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 8

https://gcc.gnu.org/g:c353bc5060d1262fbbbce50ca40950aff94eae8b commit c353bc5060d1262fbbbce50ca40950aff94eae8b Author: Pan Li Date: Wed Jun 19 20:38:43 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 8 After the middle-end support the form 8 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 7

https://gcc.gnu.org/g:52b0df31d76219a31544e4e13245e4008fdaf2a2 commit 52b0df31d76219a31544e4e13245e4008fdaf2a2 Author: Pan Li Date: Wed Jun 19 20:28:11 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 7 After the middle-end support the form 7 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6

https://gcc.gnu.org/g:8106040edb37de446a9a69d282cce6abf5b9d5d2 commit 8106040edb37de446a9a69d282cce6abf5b9d5d2 Author: Pan Li Date: Wed Jun 19 20:15:27 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 6 After the middle-end support the form 6 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 5

https://gcc.gnu.org/g:7ec128fd9d9a9b49bde6c0b2c1adef53b99f994c commit 7ec128fd9d9a9b49bde6c0b2c1adef53b99f994c Author: Pan Li Date: Wed Jun 19 19:44:52 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 5 After the middle-end support the form 5 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 4

https://gcc.gnu.org/g:f48f96bb2b8550eea44e20cd0c3c6527cac9d113 commit f48f96bb2b8550eea44e20cd0c3c6527cac9d113 Author: Pan Li Date: Wed Jun 19 19:19:23 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 4 After the middle-end support the form 4 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3

https://gcc.gnu.org/g:bee6a1a5ac883bd46255beac7d697720bc31e1f9 commit bee6a1a5ac883bd46255beac7d697720bc31e1f9 Author: Pan Li Date: Wed Jun 19 18:56:51 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 After the middle-end support the form 3 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 8

https://gcc.gnu.org/g:3d488579847638423bc7884c1752a2fb229a0cce commit 3d488579847638423bc7884c1752a2fb229a0cce Author: Pan Li Date: Mon Jun 17 22:31:27 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 8 After the middle-end support the form 8 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 7

https://gcc.gnu.org/g:ae1d941508525968a96ed93fdd3eaa28f77b3497 commit ae1d941508525968a96ed93fdd3eaa28f77b3497 Author: Pan Li Date: Mon Jun 17 22:19:54 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 7 After the middle-end support the form 7 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

https://gcc.gnu.org/g:d3690c6e2ec10ad3970f209ce656e399386a8e3e commit d3690c6e2ec10ad3970f209ce656e399386a8e3e Author: Pan Li Date: Mon Jun 17 22:10:31 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 6 After the middle-end support the form 6 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 5

https://gcc.gnu.org/g:684d632a2c4c4e230a972ae6f8864e95970aa530 commit 684d632a2c4c4e230a972ae6f8864e95970aa530 Author: Pan Li Date: Mon Jun 17 16:31:26 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 5 After the middle-end support the form 5 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 4

https://gcc.gnu.org/g:6eae8ad3a3018078fe7e8c662d40a950d022c4fb commit 6eae8ad3a3018078fe7e8c662d40a950d022c4fb Author: Pan Li Date: Mon Jun 17 16:09:13 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 4 After the middle-end support the form 4 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 3

https://gcc.gnu.org/g:120e57ec19349598b87b51d81c248537a256449c commit 120e57ec19349598b87b51d81c248537a256449c Author: Pan Li Date: Mon Jun 17 14:53:12 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 3 After the middle-end support the form 3 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2

https://gcc.gnu.org/g:ae07eb2afcc0c17759ca52ead3067b000787a115 commit ae07eb2afcc0c17759ca52ead3067b000787a115 Author: Pan Li Date: Mon Jun 17 14:39:10 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 After the middle-end support the form 2 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

https://gcc.gnu.org/g:13eae3ea598541647de32a3a81b6188403990565 commit 13eae3ea598541647de32a3a81b6188403990565 Author: Pan Li Date: Tue Jun 18 16:22:59 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12 After the middle-end support the form 12 of unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11

https://gcc.gnu.org/g:0fe89b64995618351f6e0bc05e7c2fad886a3b74 commit 0fe89b64995618351f6e0bc05e7c2fad886a3b74 Author: Pan Li Date: Tue Jun 18 16:14:23 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11 After the middle-end support the form 11 of unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move mode assertion out of conditional branch in emit_insn

https://gcc.gnu.org/g:47b3c4c862f9ce04becda9ab82d28d2f6e54d4f7 commit 47b3c4c862f9ce04becda9ab82d28d2f6e54d4f7 Author: Edwin Lu Date: Fri Jun 14 09:46:01 2024 -0700 RISC-V: Move mode assertion out of conditional branch in emit_insn When emitting insns, we have an early assertion

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vwsll combine on rv32 targets

https://gcc.gnu.org/g:23840c32e5f3bae1f23dc25a10567e50b31b73db commit 23840c32e5f3bae1f23dc25a10567e50b31b73db Author: Edwin Lu Date: Tue Jun 11 13:50:02 2024 -0700 RISC-V: Fix vwsll combine on rv32 targets On rv32 targets, vwsll_zext1_scalar_ would trigger an ice in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix wrong patch application

https://gcc.gnu.org/g:835bf804a95f0abe3ce09defb98fd11171fedff0 commit 835bf804a95f0abe3ce09defb98fd11171fedff0 Author: Jeff Law Date: Tue Jun 18 12:10:57 2024 -0600 [committed] [RISC-V] Fix wrong patch application Applied the wrong patch which didn't have the final testsuite

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve bset generation when bit position is limited

https://gcc.gnu.org/g:5a8ee7da0905b4c6b9fb9876783a5273d7eda938 commit 5a8ee7da0905b4c6b9fb9876783a5273d7eda938 Author: Jeff Law Date: Tue Jun 18 06:40:40 2024 -0600 [to-be-committed,RISC-V] Improve bset generation when bit position is limited So more work in the ongoing effort

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Handle zero_extract destination for single bit insertions

https://gcc.gnu.org/g:bd78d15abf96a90bb4e2a2f3b2cc6dc638c5ed4b commit bd78d15abf96a90bb4e2a2f3b2cc6dc638c5ed4b Author: Jeff Law Date: Mon Jun 17 17:24:03 2024 -0600 [to-be-committed,RISC-V] Handle zero_extract destination for single bit insertions Combine will use zero_extract

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add configure check for Zaamo/Zalrsc assembler support

https://gcc.gnu.org/g:6af1fde98e28478caa796904fee52be30f14f0e5 commit 6af1fde98e28478caa796904fee52be30f14f0e5 Author: Patrick O'Neill Date: Mon Jun 17 09:46:05 2024 -0700 RISC-V: Add configure check for Zaamo/Zalrsc assembler support Binutils 2.42 and before don't support

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve variable bit set for rv64

https://gcc.gnu.org/g:e0b2a59719a3807695c05681114324dc4b31570f commit e0b2a59719a3807695c05681114324dc4b31570f Author: Jeff Law Date: Mon Jun 17 07:04:13 2024 -0600 [to-be-committed,RISC-V] Improve variable bit set for rv64 Another case of being able to safely use bset for 1 <<

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64

https://gcc.gnu.org/g:13a6b20e991ece33f4f016780549bb16a5a00796 commit 13a6b20e991ece33f4f016780549bb16a5a00796 Author: Jeff Law Date: Sun Jun 16 08:36:27 2024 -0600 [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64 Another improvement for generating Zbs instructions.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for vector unsigned SAT_SUB form 2

https://gcc.gnu.org/g:f8ebe0324e14cbc528d8f6f26858969385aa14ae commit f8ebe0324e14cbc528d8f6f26858969385aa14ae Author: Pan Li Date: Sat Jun 15 20:27:01 2024 +0800 RISC-V: Add testcases for vector unsigned SAT_SUB form 2 The previous RISC-V backend .SAT_SUB enabling patch missed

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] riscv: Allocate enough space to strcpy() string

https://gcc.gnu.org/g:29b591a941e426e15a9ef4c72f5acfdf58618909 commit 29b591a941e426e15a9ef4c72f5acfdf58618909 Author: Christoph Müllner Date: Fri Jun 14 20:37:04 2024 +0200 riscv: Allocate enough space to strcpy() string I triggered an ICE on Ubuntu 24.04 when compiling code

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the SAT_ARITH test help header files [NFC]

https://gcc.gnu.org/g:252ef61a865a67c63cf40fd93594efee559de339 commit 252ef61a865a67c63cf40fd93594efee559de339 Author: Pan Li Date: Sat Jun 15 10:15:17 2024 +0800 RISC-V: Refine the SAT_ARITH test help header files [NFC] Separate the vector part code to one standalone header

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10

https://gcc.gnu.org/g:ef69f0b9b9af014df3209e787c6e37c301f4f222 commit ef69f0b9b9af014df3209e787c6e37c301f4f222 Author: Pan Li Date: Fri Jun 14 10:08:59 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 10 After the middle-end support the form 10 of unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8

https://gcc.gnu.org/g:50afa42a634f3b6de549ef7de413b4bc8ff0bc84 commit 50afa42a634f3b6de549ef7de413b4bc8ff0bc84 Author: Pan Li Date: Fri Jun 14 09:57:22 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 8 After the middle-end support the form 8 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9

https://gcc.gnu.org/g:6354e412f4b4f969e1360fad98be392177da3fa8 commit 6354e412f4b4f969e1360fad98be392177da3fa8 Author: Pan Li Date: Fri Jun 14 10:03:15 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 9 After the middle-end support the form 9 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7

https://gcc.gnu.org/g:daeb32580f74d0dde79a1eb79b4bec9a6f444f74 commit daeb32580f74d0dde79a1eb79b4bec9a6f444f74 Author: Pan Li Date: Fri Jun 14 09:49:22 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 7 After the middle-end support the form 7 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6

https://gcc.gnu.org/g:6c3406f0f00c2ccf8a5b5e6baf050bfa22579f96 commit 6c3406f0f00c2ccf8a5b5e6baf050bfa22579f96 Author: Pan Li Date: Thu Jun 13 23:05:00 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 6 After the middle-end support the form 6 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5

https://gcc.gnu.org/g:094e1b811fbd009bca7db60e026ff811ee9551e4 commit 094e1b811fbd009bca7db60e026ff811ee9551e4 Author: Pan Li Date: Thu Jun 13 22:43:31 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 5 After the middle-end support the form 5 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch

https://gcc.gnu.org/g:1aa0928ed9fd4e24dcad9ac5099c70395642883d commit 1aa0928ed9fd4e24dcad9ac5099c70395642883d Author: Pan Li Date: Fri Jun 14 14:54:22 2024 +0800 RISC-V: Bugfix vec_extract v mode iterator restriction mismatch We have vec_extract pattern which takes ZVFHMIN as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4

https://gcc.gnu.org/g:ea6644ded5cd2df55c0cb37a7e21aeecd7a7e3a4 commit ea6644ded5cd2df55c0cb37a7e21aeecd7a7e3a4 Author: Pan Li Date: Thu Jun 13 22:35:21 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 4 After the middle-end support the form 4 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

https://gcc.gnu.org/g:c63393401c5da881828997484e73bd4f012caaee commit c63393401c5da881828997484e73bd4f012caaee Author: Pan Li Date: Thu Jun 13 22:06:09 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 After the middle-end support the form 3 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support for subword atomic loads/stores

https://gcc.gnu.org/g:04989c678e2a2066d486443eb1045247a0ec20a3 commit 04989c678e2a2066d486443eb1045247a0ec20a3 Author: Patrick O'Neill Date: Wed Jun 12 17:10:13 2024 -0700 RISC-V: Add support for subword atomic loads/stores Andrea Parri recently pointed out that we were emitting

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch

https://gcc.gnu.org/g:e80e1db5a63ef41b5477fb80130e556f548db588 commit e80e1db5a63ef41b5477fb80130e556f548db588 Author: Pan Li Date: Thu Jun 13 15:26:59 2024 +0800 RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch We have vec_extract pattern which takes ZVFHMIN as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Test: Move target independent test cases to gcc.dg/torture

https://gcc.gnu.org/g:a457cce60e7031e08e7795ae41819f2929e83fa5 commit a457cce60e7031e08e7795ae41819f2929e83fa5 Author: Pan Li Date: Tue Jun 11 10:56:23 2024 +0800 Test: Move target independent test cases to gcc.dg/torture The test cases of pr115387 are target independent, at

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow any temp register to be used in amo tests

https://gcc.gnu.org/g:92e22468413a16b10ff08c7c3674475f6f8d2976 commit 92e22468413a16b10ff08c7c3674475f6f8d2976 Author: Patrick O'Neill Date: Mon Jun 10 17:00:38 2024 -0700 RISC-V: Allow any temp register to be used in amo tests We artifically restrict the temp registers to be

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix amoadd call arguments

https://gcc.gnu.org/g:759a34e3f26367ce0b2eabd38f8fd03f7bada664 commit 759a34e3f26367ce0b2eabd38f8fd03f7bada664 Author: Patrick O'Neill Date: Mon Jun 10 16:58:12 2024 -0700 RISC-V: Fix amoadd call arguments Update __atomic_add_fetch arguments to be a pointer and value rather

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move amo tests into subfolder

https://gcc.gnu.org/g:9f9724b6a33d39b32d484e4eabe14097a412320c commit 9f9724b6a33d39b32d484e4eabe14097a412320c Author: Patrick O'Neill Date: Mon Jun 10 16:32:11 2024 -0700 RISC-V: Move amo tests into subfolder There's a large number of atomic related testcases in the riscv

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zalrsc amo-op patterns

https://gcc.gnu.org/g:a120ea65ca23b0436f58b99cf30e35c6f1ec9bf3 commit a120ea65ca23b0436f58b99cf30e35c6f1ec9bf3 Author: Patrick O'Neill Date: Wed Feb 7 16:30:30 2024 -0800 RISC-V: Add Zalrsc amo-op patterns All amo patterns can be represented with lrsc sequences. Add these

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zalrsc and Zaamo testsuite support

https://gcc.gnu.org/g:b11365101a0e6afc5bae847d368636ef99a98964 commit b11365101a0e6afc5bae847d368636ef99a98964 Author: Patrick O'Neill Date: Mon Jun 10 14:12:40 2024 -0700 RISC-V: Add Zalrsc and Zaamo testsuite support Convert testsuite infrastructure to use Zalrsc and Zaamo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add basic Zaamo and Zalrsc support

https://gcc.gnu.org/g:73cd4403af9bdfd81c24741a2afac1b53597e148 commit 73cd4403af9bdfd81c24741a2afac1b53597e148 Author: Edwin Lu Date: Wed Feb 7 16:30:28 2024 -0800 RISC-V: Add basic Zaamo and Zalrsc support There is a proposal to split the A extension into two parts: Zaamo and

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_SUB for unsigned vector int

https://gcc.gnu.org/g:de50942b26eaaf91b472fb6cbb29201476c9dcb3 commit de50942b26eaaf91b472fb6cbb29201476c9dcb3 Author: Pan Li Date: Tue Jun 11 11:04:22 2024 +0800 RISC-V: Implement .SAT_SUB for unsigned vector int As the middle support of .SAT_SUB committed, implement the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Drop dead round_32 test

https://gcc.gnu.org/g:95948af9727cfa8dc6709b4d5719011efc5c47a7 commit 95948af9727cfa8dc6709b4d5719011efc5c47a7 Author: Jeff Law Date: Mon Jun 10 22:39:40 2024 -0600 [committed] [RISC-V] Drop dead round_32 test This test is no longer useful. It doesn't test what it was originally

[gcc r15-1574] [PATCH 06/11] Handle enums for CodeView

https://gcc.gnu.org/g:d820db38870155d941ffcad5846389e0de059534 commit r15-1574-gd820db38870155d941ffcad5846389e0de059534 Author: Mark Harmstone Date: Sun Jun 23 21:48:22 2024 -0600 [PATCH 06/11] Handle enums for CodeView Translates DW_TAG_enumeration_type DIEs into LF_ENUM

[gcc r15-1573] [PATCH 05/11] Handle const and varible modifiers for CodeView

https://gcc.gnu.org/g:29fec9ee74c3219bce714f2e5b6381a48049e01e commit r15-1573-g29fec9ee74c3219bce714f2e5b6381a48049e01e Author: Mark Harmstone Date: Sun Jun 23 21:39:45 2024 -0600 [PATCH 05/11] Handle const and varible modifiers for CodeView gcc/ * dwarf2codeview.cc

[gcc r15-1572] [PATCH 04/11] Handle pointers for CodeView

https://gcc.gnu.org/g:35cca2ccd908960d789533ddb93bb1bea5e71305 commit r15-1572-g35cca2ccd908960d789533ddb93bb1bea5e71305 Author: Mark Harmstone Date: Sun Jun 23 21:30:08 2024 -0600 [PATCH 04/11] Handle pointers for CodeView Translates DW_TAG_pointer_type DIEs into LF_POINTER

[gcc r15-1571] [PATCH 03/11] Handle typedefs for CodeView

https://gcc.gnu.org/g:de2ade6908c6f18b821d6d25b4f4833c850fa19c commit r15-1571-gde2ade6908c6f18b821d6d25b4f4833c850fa19c Author: Mark Harmstone Date: Sun Jun 23 18:30:02 2024 -0600 [PATCH 03/11] Handle typedefs for CodeView gcc/ * dwarf2codeview.cc (get_type_num):

[gcc r15-1570] [PATCH 02/11] Handle CodeView base types

https://gcc.gnu.org/g:340bca65ce50ccb827a2501273f50da77c7d7349 commit r15-1570-g340bca65ce50ccb827a2501273f50da77c7d7349 Author: Mark Harmstone Date: Sun Jun 23 18:17:39 2024 -0600 [PATCH 02/11] Handle CodeView base types Adds a get_type_num function to translate type DIEs into

[gcc r15-1568] [PATCH 01/11] Output CodeView data about variables

https://gcc.gnu.org/g:a9df6bdef485a185a0911d103e7a456c2f22c16a commit r15-1568-ga9df6bdef485a185a0911d103e7a456c2f22c16a Author: Mark Harmstone Date: Sun Jun 23 17:48:10 2024 -0600 [PATCH 01/11] Output CodeView data about variables Parse the DW_TAG_variable DIEs, and outputs

[gcc r15-1567] [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move()

https://gcc.gnu.org/g:eb647daa87b466d0a71246fad302cd81bfce9be5 commit r15-1567-geb647daa87b466d0a71246fad302cd81bfce9be5 Author: Artemiy Volkov Date: Sun Jun 23 14:54:00 2024 -0600 [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move() Presently, the code

[gcc r15-1566] [committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extracting INTVAL

https://gcc.gnu.org/g:fd536b8412d4dae42aa04739c06f99a915be6261 commit r15-1566-gfd536b8412d4dae42aa04739c06f99a915be6261 Author: Jeff Law Date: Sun Jun 23 08:26:25 2024 -0600 [committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extracting INTVAL

[gcc r15-1562] [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests

https://gcc.gnu.org/g:77f3b3419d476e90a2b82dff2204466aba3b9c2c commit r15-1562-g77f3b3419d476e90a2b82dff2204466aba3b9c2c Author: Craig Blackmore Date: Sat Jun 22 22:07:06 2024 -0600 [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests These tests check the sched2 dump, so skip them

[gcc r15-1561] [PATCH v2] RISC-V: Remove integer vector eqne pattern

https://gcc.gnu.org/g:dba21b6a4085506fe730f2ff5d9b56f5944223bf commit r15-1561-gdba21b6a4085506fe730f2ff5d9b56f5944223bf Author: demin.han Date: Sat Jun 22 22:02:02 2024 -0600 [PATCH v2] RISC-V: Remove integer vector eqne pattern We can unify eqne and other comparison operations.

[gcc r15-1559] [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well

https://gcc.gnu.org/g:6ceb5f7859e3fe39feb62de402bed656b8dfe6b9 commit r15-1559-g6ceb5f7859e3fe39feb62de402bed656b8dfe6b9 Author: Jeff Law Date: Sat Jun 22 10:39:51 2024 -0600 [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well > the test should probably also be skipped on -Oz:

[gcc r15-1554] [committed] Fix testsuite fallout on stormy16 after IOR->PLUS change

https://gcc.gnu.org/g:37f3000a57d62b808188eb6a14a369f6a789e1ea commit r15-1554-g37f3000a57d62b808188eb6a14a369f6a789e1ea Author: Jeff Law Date: Fri Jun 21 15:58:12 2024 -0600 [committed] Fix testsuite fallout on stormy16 after IOR->PLUS change More minor fallout from the

[gcc r15-1501] [RISC-V] Minor cleanup/improvement to bset/binv patterns

https://gcc.gnu.org/g:f739ad5e35b0a60dec65bb12f8d07aadd0c98196 commit r15-1501-gf739ad5e35b0a60dec65bb12f8d07aadd0c98196 Author: Jeff Law Date: Thu Jun 20 08:43:37 2024 -0600 [RISC-V] Minor cleanup/improvement to bset/binv patterns Changes since V1: Whitespace fixes

[gcc r15-1457] [PATCH v2] RISC-V: Remove float vector eqne pattern

https://gcc.gnu.org/g:f0204ae3861e5f2e6099719c2cb1718e064c8c12 commit r15-1457-gf0204ae3861e5f2e6099719c2cb1718e064c8c12 Author: demin.han Date: Wed Jun 19 16:21:13 2024 -0600 [PATCH v2] RISC-V: Remove float vector eqne pattern We can unify eqne and other comparison operations.

[gcc r15-1419] [committed] [RISC-V] Fix wrong patch application

https://gcc.gnu.org/g:cbf7245c8b305fe997a535051a4fec379a429243 commit r15-1419-gcbf7245c8b305fe997a535051a4fec379a429243 Author: Jeff Law Date: Tue Jun 18 12:10:57 2024 -0600 [committed] [RISC-V] Fix wrong patch application Applied the wrong patch which didn't have the final

[gcc r15-1406] [to-be-committed, RISC-V] Improve bset generation when bit position is limited

https://gcc.gnu.org/g:a78e2c3a00d8b147b44416f7a843c9df61f04531 commit r15-1406-ga78e2c3a00d8b147b44416f7a843c9df61f04531 Author: Jeff Law Date: Tue Jun 18 06:40:40 2024 -0600 [to-be-committed,RISC-V] Improve bset generation when bit position is limited So more work in the

[gcc r15-1386] [to-be-committed, RISC-V] Handle zero_extract destination for single bit insertions

https://gcc.gnu.org/g:67bc21af7ba35b773b5cf0e85107715f7c2240e4 commit r15-1386-g67bc21af7ba35b773b5cf0e85107715f7c2240e4 Author: Jeff Law Date: Mon Jun 17 17:24:03 2024 -0600 [to-be-committed,RISC-V] Handle zero_extract destination for single bit insertions Combine will use

[gcc r15-1376] [to-be-committed, RISC-V] Improve variable bit set for rv64

https://gcc.gnu.org/g:83aad89fb99d0e82209734717c12f5aaca477970 commit r15-1376-g83aad89fb99d0e82209734717c12f5aaca477970 Author: Jeff Law Date: Mon Jun 17 07:04:13 2024 -0600 [to-be-committed,RISC-V] Improve variable bit set for rv64 Another case of being able to safely use bset

[gcc r15-1358] [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64

https://gcc.gnu.org/g:59dfce6d618ccf5865dec216603dbc25a4f7bf2d commit r15-1358-g59dfce6d618ccf5865dec216603dbc25a4f7bf2d Author: Jeff Law Date: Sun Jun 16 08:36:27 2024 -0600 [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64 Another improvement for generating Zbs

[gcc r15-1357] [committed] Fix minor SH scan-asm failure after recent IOR->ADD changes

https://gcc.gnu.org/g:0240909cb03f2a37a74364b00e51ad782c748551 commit r15-1357-g0240909cb03f2a37a74364b00e51ad782c748551 Author: Jeff Law Date: Sat Jun 15 21:17:10 2024 -0600 [committed] Fix minor SH scan-asm failure after recent IOR->ADD changes This fixes minor fallout from the

[gcc r15-1172] [committed] [RISC-V] Drop dead round_32 test

https://gcc.gnu.org/g:95161c6abfbd7ba9fab0b538ccc885f5980efbee commit r15-1172-g95161c6abfbd7ba9fab0b538ccc885f5980efbee Author: Jeff Law Date: Mon Jun 10 22:39:40 2024 -0600 [committed] [RISC-V] Drop dead round_32 test This test is no longer useful. It doesn't test what it was

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:08a6582277f62c1b5873dfa4d385a2b2e8843d8f commit 08a6582277f62c1b5873dfa4d385a2b2e8843d8f Author: Raphael Zinsly Date: Mon Jun 10 14:16:16 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as (src >> n)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Just the testsuite bits from:

https://gcc.gnu.org/g:1d97b9d17699ea5fdd0945b8ce8aecda79829ff4 commit 1d97b9d17699ea5fdd0945b8ce8aecda79829ff4 Author: Pan Li Date: Mon Jun 10 14:13:38 2024 -0600 Just the testsuite bits from: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match When

[gcc r15-1168] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:9aaf29b9ba5ffe332220d002ddde85d96fd6657d commit r15-1168-g9aaf29b9ba5ffe332220d002ddde85d96fd6657d Author: Raphael Zinsly Date: Mon Jun 10 14:16:16 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as

[gcc r15-1167] [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

https://gcc.gnu.org/g:d03ff3fd3e2da1352a404e3c53fe61314569345c commit r15-1167-gd03ff3fd3e2da1352a404e3c53fe61314569345c Author: Pan Li Date: Mon Jun 10 14:13:38 2024 -0600 [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match When enabled the PHI handing for

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:c5c054c429ac5a4d1a665d6e5e4634973dffae5a commit c5c054c429ac5a4d1a665d6e5e4634973dffae5a Author: Raphael Zinsly Date: Mon Jun 10 07:03:00 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as (src >> n)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14

https://gcc.gnu.org/g:7cf4c1e16755f7adab3bff983d980d6ae0b9a6f3 commit 7cf4c1e16755f7adab3bff983d980d6ae0b9a6f3 Author: Andreas Tobler Date: Sun Jun 9 23:18:04 2024 +0200 FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14 As of FreeBSD version 14, FreeBSD no longer provides

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix false-positive uninitialized variable

https://gcc.gnu.org/g:e0a5507e6888f85e2ff53aff76c67293890bed85 commit e0a5507e6888f85e2ff53aff76c67293890bed85 Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit warning after

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

https://gcc.gnu.org/g:21b9c1625d9178475ebbb7d524923e421a93906d commit 21b9c1625d9178475ebbb7d524923e421a93906d Author: Roger Sayle Date: Sat Jun 8 19:47:08 2024 -0600 [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates. This patch tweaks RTL

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_SUB for unsigned scalar int

https://gcc.gnu.org/g:d63ee880aa3931d37fe73570d3a41952daafd8ee commit d63ee880aa3931d37fe73570d3a41952daafd8ee Author: Pan Li Date: Wed Jun 5 16:42:05 2024 +0800 RISC-V: Implement .SAT_SUB for unsigned scalar int As the middle support of .SAT_SUB committed, implement the

[gcc r15-1164] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:3472c1b500cf9184766237bfd3d102aa8451b99f commit r15-1164-g3472c1b500cf9184766237bfd3d102aa8451b99f Author: Raphael Zinsly Date: Mon Jun 10 07:03:00 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as

[gcc r15-1123] [committed] [RISC-V] Fix false-positive uninitialized variable

https://gcc.gnu.org/g:932c6f8dd8859afb13475c2de466bd1a159530da commit r15-1123-g932c6f8dd8859afb13475c2de466bd1a159530da Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit

[gcc r15-1120] [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

https://gcc.gnu.org/g:2277f987979445f4390a5c6e092d79e04814d641 commit r15-1120-g2277f987979445f4390a5c6e092d79e04814d641 Author: Roger Sayle Date: Sat Jun 8 19:47:08 2024 -0600 [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates. This patch

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 3

https://gcc.gnu.org/g:4b3c0b3380d38553e76bbf01e1ac5b3f66dc3d5c commit 4b3c0b3380d38553e76bbf01e1ac5b3f66dc3d5c Author: Pan Li Date: Mon Jun 3 10:24:47 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 3 After the middle-end support the form 3 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1

https://gcc.gnu.org/g:efe00579c04e02b6132c678962ce8050c8759bee commit efe00579c04e02b6132c678962ce8050c8759bee Author: Pan Li Date: Wed May 29 14:15:45 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 After the middle-end support the form 1 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Regenerate opt urls.

https://gcc.gnu.org/g:4f20feccf708ff7a7af5d776ca87d4995ef46f76 commit 4f20feccf708ff7a7af5d776ca87d4995ef46f76 Author: Robin Dapp Date: Thu Jun 6 09:32:28 2024 +0200 RISC-V: Regenerate opt urls. I wasn't aware that I needed to regenerate the opt urls when adding an option.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 5

https://gcc.gnu.org/g:1a6d2ed7fbd20bfa3079da4700eb591f2abaa395 commit 1a6d2ed7fbd20bfa3079da4700eb591f2abaa395 Author: Pan Li Date: Mon Jun 3 10:43:10 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 5 After the middle-end support the form 5 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 2

https://gcc.gnu.org/g:6f5119eed91a2ec0708e38c9f2e5d58169a3f53e commit 6f5119eed91a2ec0708e38c9f2e5d58169a3f53e Author: Pan Li Date: Mon Jun 3 09:35:49 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 2 After the middle-end support the form 2 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 4

https://gcc.gnu.org/g:b93df02d58c0c448c4b524c07bdf5f3d7c305378 commit b93df02d58c0c448c4b524c07bdf5f3d7c305378 Author: Pan Li Date: Mon Jun 3 10:33:15 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 4 After the middle-end support the form 4 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode.

https://gcc.gnu.org/g:e46fc82745c1a917ade318222d514c881c68ce1a commit e46fc82745c1a917ade318222d514c881c68ce1a Author: liuhongt Date: Fri Apr 19 10:29:34 2024 +0800 Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode. When mask is (1 << (prec - imm) - 1)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Introduce -mvector-strict-align.

https://gcc.gnu.org/g:0e0b666a30f53364292432903b68febd85a3e114 commit 0e0b666a30f53364292432903b68febd85a3e114 Author: Robin Dapp Date: Tue May 28 21:19:26 2024 +0200 RISC-V: Introduce -mvector-strict-align. this patch disables movmisalign by default and introduces the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zfbfmin extension

https://gcc.gnu.org/g:f11cbf2edfbd9615cf0d8519bd7a570a2ae00397 commit f11cbf2edfbd9615cf0d8519bd7a570a2ae00397 Author: Xiao Zeng Date: Wed May 15 13:56:42 2024 +0800 RISC-V: Add Zfbfmin extension 1 In the previous patch, the libcall for BF16 was implemented:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE

https://gcc.gnu.org/g:6eb2b8506e4123b00c32b8a23bafdee4c8c8b7f8 commit 6eb2b8506e4123b00c32b8a23bafdee4c8c8b7f8 Author: Jiawei Date: Mon May 27 15:40:51 2024 +0800 tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE when deal special cases.

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