https://gcc.gnu.org/g:642cfd049780f03335da9fe0a51415f130232334
commit r12-10329-g642cfd049780f03335da9fe0a51415f130232334
Author: Tamar Christina <tamar.christ...@arm.com>
Date: Mon Apr 15 12:16:53 2024 +0100
AArch64: Do not allow SIMD clones with simdlen 1 [PR113552]
This is a backport of g:306713c953d509720dc394c43c0890548bb0ae07.
The AArch64 vector PCS does not allow simd calls with simdlen 1,
however due to a bug we currently do allow it for num == 0.
This causes us to emit a symbol that doesn't exist and we fail to link.
gcc/ChangeLog:
PR tree-optimization/113552
* config/aarch64/aarch64.cc
(aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
gcc/testsuite/ChangeLog:
PR tree-optimization/113552
* gcc.target/aarch64/pr113552.c: New test.
* gcc.target/aarch64/simd_pcs_attribute-3.c: Remove bogus check.
Diff:
---
gcc/config/aarch64/aarch64.cc | 16 +++++++++++++---
gcc/testsuite/gcc.target/aarch64/pr113552.c | 17 +++++++++++++++++
gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c | 4 ++--
3 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 2bbba323770..96976abdbf4 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -26898,7 +26898,7 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct
cgraph_node *node,
tree base_type, int num)
{
tree t, ret_type;
- unsigned int elt_bits, count;
+ unsigned int elt_bits, count = 0;
unsigned HOST_WIDE_INT const_simdlen;
poly_uint64 vec_bits;
@@ -26966,8 +26966,17 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct
cgraph_node *node,
elt_bits = GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type));
if (known_eq (clonei->simdlen, 0U))
{
- count = 2;
- vec_bits = (num == 0 ? 64 : 128);
+ /* We don't support simdlen == 1. */
+ if (known_eq (elt_bits, 64))
+ {
+ count = 1;
+ vec_bits = 128;
+ }
+ else
+ {
+ count = 2;
+ vec_bits = (num == 0 ? 64 : 128);
+ }
clonei->simdlen = exact_div (vec_bits, elt_bits);
}
else
@@ -26985,6 +26994,7 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct
cgraph_node *node,
return 0;
}
}
+
clonei->vecsize_int = vec_bits;
clonei->vecsize_float = vec_bits;
return count;
diff --git a/gcc/testsuite/gcc.target/aarch64/pr113552.c
b/gcc/testsuite/gcc.target/aarch64/pr113552.c
new file mode 100644
index 00000000000..9c96b061ed2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr113552.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast -march=armv8-a" } */
+
+__attribute__ ((__simd__ ("notinbranch"), const))
+double cos (double);
+
+void foo (float *a, double *b)
+{
+ for (int i = 0; i < 12; i+=3)
+ {
+ b[i] = cos (5.0 * a[i]);
+ b[i+1] = cos (5.0 * a[i+1]);
+ b[i+2] = cos (5.0 * a[i+2]);
+ }
+}
+
+/* { dg-final { scan-assembler-times {bl\t_ZGVnN2v_cos} 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
b/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
index 95f6a6803e8..c6dac6b104c 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c
@@ -18,7 +18,7 @@ double foo(double x)
}
/* { dg-final { scan-assembler-not {\.variant_pcs\tfoo} } } */
-/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnM1v_foo} 1 } } */
+/* { dg-final { scan-assembler-not {\.variant_pcs\t_ZGVnM1v_foo} } } */
/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnM2v_foo} 1 } } */
-/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnN1v_foo} 1 } } */
+/* { dg-final { scan-assembler-not {\.variant_pcs\t_ZGVnN1v_foo} } } */
/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnN2v_foo} 1 } } */
