https://gcc.gnu.org/g:a2026fb10fd00c5c6a7e262f8d5966f96ec8e49a
commit a2026fb10fd00c5c6a7e262f8d5966f96ec8e49a
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Apr 10 12:08:48 2024 -0400
Improve 64->128 bit zero extension on PowerPC (PR target/108958)
If we are converting an unsigned DImode to a TImode value, and the TImode
value
will go in a vector register, GCC currently does the DImode to TImode
conversion
in GPR registers, and then moves the value to the vector register via a
mtvsrdd
instruction.
This patch adds a new zero_extendditi2 insn which optimizes moving a GPR to
a
vector register using the mtvsrdd instruction with RA=0, and using lxvrdx to
load a 64-bit value into the bottom 64-bits of the vector register.
I have tested this patch on the following systems and there was no
degration.
Can I check it into the trunk branch?
* Power10, LE, --with-cpu=power10, IBM 128-bit long double
* Power9, LE, --with-cpu=power9, IBM 128-bit long double
* Power9, LE, --with-cpu=power9, IEEE 128-bit long double
* Power9, LE, --with-cpu=power9, 64-bit default long double
* Power9, BE, --with-cpu=power9, IBM 128-bit long double
* Power8, BE, --with-cpu=power8, IBM 128-bit long double
2024-04-10 Michael Meissner <meiss...@linux.ibm.com>
gcc/
PR target/108958
* gcc/config/rs6000.md (zero_extendditi2): New insn.
gcc/testsuite/
PR target/108958
* gcc.target/powerpc/pr108958.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.md | 52 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/powerpc/pr108958.c | 57 +++++++++++++++++++++++++++++
2 files changed, 109 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f626b68ebb2..f1f120199f3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -994,6 +994,58 @@
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
+(define_insn_and_split "zero_extendditi2"
+ [(set (match_operand:TI 0 "gpc_reg_operand" "=r,r,wa,wa,wa")
+ (zero_extend:TI
+ (match_operand:DI 1 "reg_or_mem_operand" "r,m,b,Z,wa")))
+ (clobber (match_scratch:DI 2 "=X,X,X,X,&wa"))]
+ "TARGET_POWERPC64 && TARGET_P9_VECTOR"
+ "@
+ #
+ #
+ mtvsrdd %x0,0,%1
+ lxvrdx %x0,%y1
+ #"
+ "&& reload_completed
+ && (int_reg_operand (operands[0], TImode)
+ || (vsx_register_operand (operands[0], TImode)
+ && vsx_register_operand (operands[1], DImode)))"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 3) (const_int 0))]
+{
+ rtx dest = operands[0];
+ rtx src = operands[1];
+
+ /* If we are converting a VSX DImode to VSX TImode, we need to move the upper
+ 64-bits (DImode) to the lower 64-bits. We can't just do a xxpermdi
+ instruction to swap the two 64-bit words, because can't rely on the bottom
+ 64-bits of the VSX register being 0. Instead we create a 0 and do the
+ xxpermdi operation to combine the two registers. */
+ if (vsx_register_operand (dest, TImode)
+ && vsx_register_operand (src, DImode))
+ {
+ rtx tmp = operands[2];
+ emit_move_insn (tmp, const0_rtx);
+
+ rtx hi = tmp;
+ rtx lo = src;
+ if (!BYTES_BIG_ENDIAN)
+ std::swap (hi, lo);
+
+ rtx dest_v2di = gen_rtx_REG (V2DImode, reg_or_subregno (dest));
+ emit_insn (gen_vsx_concat_v2di (dest_v2di, hi, lo));
+ DONE;
+ }
+
+ /* If we are zero extending to a GPR register either from a GPR register,
+ a VSX register or from memory, do the zero extend operation to the
+ lower DI register, and set the upper DI register to 0. */
+ operands[2] = gen_lowpart (DImode, dest);
+ operands[3] = gen_highpart (DImode, dest);
+}
+ [(set_attr "type" "*,load,vecexts,vecload,vecperm")
+ (set_attr "isa" "*,*,p9v,p10,*")
+ (set_attr "length" "8,8,*,*,8")])
(define_insn "extendqi<mode>2"
[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr108958.c
b/gcc/testsuite/gcc.target/powerpc/pr108958.c
new file mode 100644
index 00000000000..85ea0976f91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr108958.c
@@ -0,0 +1,57 @@
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+/* This patch makes sure the various optimization and code paths are done for
+ zero extending DImode to TImode on power10 (PR target/pr108958). */
+
+__uint128_t
+gpr_to_gpr (unsigned long long a)
+{
+ return a; /* li 4,0. */
+}
+
+__uint128_t
+mem_to_gpr (unsigned long long *p)
+{
+ return *p; /* ld 3,0(3); li 4,0. */
+}
+
+__uint128_t
+vsx_to_gpr (double d)
+{
+ return (unsigned long long)d; /* fctiduz 0,1; li 4,0; mfvsrd
3,0. */
+}
+
+void
+gpr_to_vsx (__uint128_t *p, unsigned long long a)
+{
+ __uint128_t b = a; /* mtvsrdd 0,0,4; stxv 0,0(3). */
+ __asm__ (" # %x0" : "+wa" (b));
+ *p = b;
+}
+
+void
+mem_to_vsx (__uint128_t *p, unsigned long long *q)
+{
+ __uint128_t a = *q; /* lxvrdx 0,0,4; stxv 0,0(3). */
+ __asm__ (" # %x0" : "+wa" (a));
+ *p = a;
+}
+
+void
+vsx_to_vsx (__uint128_t *p, double d)
+{
+ /* fctiduz 1,1; xxspltib 0,0; xxpermdi 0,0,1,0; stxv 0,0(3). */
+ __uint128_t a = (unsigned long long)d;
+ __asm__ (" # %x0" : "+wa" (a));
+ *p = a;
+}
+
+/* { dg-final { scan-assembler-times {\mld\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mli\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlxvrdx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mmfvsrd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mmtvsrdd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxv\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
