[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:b822fba1413b1cd01f2c8331ed639f88e54f2c50 commit b822fba1413b1cd01f2c8331ed639f88e54f2c50 Author: Michael Meissner Date: Sat Nov 16 19:11:51 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 13 + 1 file changed, 13 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 5657110e7a6a..397dc8184bc9 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -164,6 +164,19 @@ gcc/testsuite/ * gcc.target/powerpc/pr87496-1.c: Update options to use -mdejagnu-cpu=power6 to get the appropriate error message. + Branch work186, patch #74 + +Vector pair test only runs in 64-bits + +In 32-bit mode, the vector pair load and stores are not generated, even if +-mcpu=future is used. Only run the future-3.c in 64-bit mode. + +2024-11-16 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/future-3.c: Limit test to 64-bit. + Branch work186, patch #73 Use vector pair load/store for memcpy with -mcpu=future
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:c361001019bc64668ac7187e91a670042109d7b9 commit c361001019bc64668ac7187e91a670042109d7b9 Author: Michael Meissner Date: Sat Nov 16 00:48:16 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 127 + 1 file changed, 127 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 49826411141c..5657110e7a6a 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,130 @@ + Branch work186, patch #91 + +Use architecture flags for defining _ARCH_PWR macros. + +For the newer architectures, this patch changes GCC to define the _ARCH_PWR +macros using the new architecture flags instead of relying on isa options like +-mpower10. + +The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were removed. +The -mpower11 and -mfuture options were removed completely, since they were just +added in GCC 15. The other two options were marked as WarnRemoved, and the +various ISA bits were removed. + +TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were re-defined +to use the architeture bits instead of the ISA bits. + +There are other internal isa bits that aren't removed with this patch because +the built-in function support uses those bits. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +Can I install this patch on the GCC 15 trunk? + +2024-11-16 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to + use architecture flags instead of ISA flags for setting most of the + _ARCH_PWR* macros. + (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call. + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove + OPTION_MASK_POWER8. + (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10. + (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11. + (FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE. + (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, + OPTION_MASK_POWER11, and OPTION_MASK_FUTURE. + * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update + declaration. + (rs6000_target_modify_macros_ptr): Likewise. + * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise. + (rs6000_option_override_internal): Use architecture flags instead of ISA + flags. + (rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which are + no longer in the ISA flags. + (rs6000_pragma_target_parse): Use architecture flags as well as ISA + flags. + * config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use architecture + flags. + (TARGET_POWER5X): Likewise. + (TARGET_POWER6): Likewise. + (TARGET_POWER7): Likewise. + (TARGET_POWER8): Likewise. + (TARGET_POWER9): Likewise. + (TARGET_POWER10): New macro. + (TARGET_POWER11): Likewise. + (TARGET_FUTRE): Likewise. + * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits. + (-mpower10): Likewise. + (-mpower11): Likewise. + (-mfuture): Likewise. + + Branch work186, patch #90 + +Add rs6000 architecture masks. + +This patch begins the journey to move architecture bits that are not user ISA +options from rs6000_isa_flags to a new targt variable rs6000_arch_flags. The +intention is to remove switches that are currently isa options, but the user +should not be using this particular option. For example, we want users to use +-mcpu=power10 and not just -mpower10. + +This patch also changes the target_clones support to use an architecture mask +instead of isa bits. + +This patch also switches the handling of .machine to use architecture masks if +they exist (power4 through power11). All of the other PowerPCs will continue to +use the existing code for setting the .machine option. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +In addition, I constructed a test case that used every archiecture define (like +_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran +this test for all supported combinations of -mcpu, big/little endian, and 32/64 +bit support. Every single instance generated exactly the same code with the +patches installed compared to the compiler before installing the patches. + +The only difference in this patch compared to the first version posted on +November 6th is that I the correct attribution and copyright year (i.e. that I +created rs6000-arch.def in 2024). + +Can I install this patch on the GCC 15 trunk? + +2024-11-16 Michael Meissner + +gcc/ + + * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name. + * config/rs6000/rs6000-arch.def: New file. + * confi
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:ae4999cc96fb6122d8054f79d1d33d76dd9954a7 commit ae4999cc96fb6122d8054f79d1d33d76dd9954a7 Author: Michael Meissner Date: Sat Nov 16 00:01:52 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 89 ++ 1 file changed, 89 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index e1242ca98867..a712a5abf213 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,92 @@ + Branch work186, patch #73 + +Use vector pair load/store for memcpy with -mcpu=future + +In the development for the power10 processor, GCC did not enable using the load +vector pair and store vector pair instructions when optimizing things like +memory copy. This patch enables using those instructions if -mcpu=future is +used. + +2024-11-16 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable using + load vector pair and store vector pair instructions for memory copy + operations. + (POWERPC_MASKS): Make the bit for enabling using load vector pair and + store vector pair operations set and reset when the PowerPC processor is + changed. + * gcc/config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable + -mblock-ops-vector-pair from influcing .machine selection. + +gcc/testsuite/ + + * gcc.target/powerpc/future-3.c: New test. + + Branch work186, patch #72 + +Add -mcpu=future tests. + +This patch adds simple tests for -mcpu=future. + +2024-11-16 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/future-1.c: New test. + * gcc.target/powerpc/future-2.c: Likewise. + + Branch work186, patch #71 + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-11-16 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work186, patch #70 + +Add support for -mcpu=future + +This patch adds the support that can be used in developing GCC support for +future PowerPC processors. + +2024-11-16 Michael Meissner + + * config.gcc (powerpc*-*-*): Add support for --with-cpu=future. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If + -mcpu=future, define _ARCH_FUTURE. + * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro. + (POWERPC_MASKS): Add OPTION_MASK_FUTURE. + (future cpu): Define. + * config/rs6000/rs6000-opts.h (enum processor_type): Add + PROCESSOR_FUTURE. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (power10_cost): Update comment. + (get_arch_flags): Add support for future processor. + (rs6000_option_override_internal): Likewise. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Add -mfuture. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Likewise. + * config/rs6000/rs6000.opt (-mfuture): New internal option. + Branch work186, patch #64 Change TARGET_MODULO to TARGET_POWER9.
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:e09abf06ad4cf771097df10a77a4eabb5184d116 commit e09abf06ad4cf771097df10a77a4eabb5184d116 Author: Michael Meissner Date: Sat Nov 16 00:09:50 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 39 +++ 1 file changed, 39 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index a712a5abf213..49826411141c 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,42 @@ + Branch work186, patch #80 + +Do not allow -mvsx to boost processor to power7. + +This patch restructures the code so that -mvsx for example will not silently +convert the processor to power7. The user must now use -mcpu=power7 or higher. +This means if the user does -mvsx and the default processor does not have VSX +support, it will be an error. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +I updated the 2 tests that used -mvsx to raise the cpu to power7, and the test +case that checks if -mno-vsx produces the expected warning. + +Note, Peter had some questions about one of the tests in the previous version of +the patch. The test is still the same in this patch. But the code for +preventing -mvsx is different from the previous patch, and I wanted to get that +patch for review before stage1 closes. + +Can I install this patch on the GCC 15 trunk? + +2024-11-16 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Check if + the user asked for VSX instructions whether the cpu was at least power7. + +gcc/testsuite/ + + * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7 + when we need to add VSX support. Add test for adding cpu=power7 no-vsx + to generate only Altivec instructions. + * gcc.target/powerpc/pr115688.c: Add cpu=power7 in target __attribute__ + when requesting VSX instructions. + * gcc.target/powerpc/pr87496-1.c: Update options to use + -mdejagnu-cpu=power6 to get the appropriate error message. + Branch work186, patch #73 Use vector pair load/store for memcpy with -mcpu=future
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:505f92e8e2609a8e60d8e70b35da86d39dc50780 commit 505f92e8e2609a8e60d8e70b35da86d39dc50780 Author: Michael Meissner Date: Fri Nov 15 22:52:37 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 147 + 1 file changed, 147 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index d3fe88717646..e1242ca98867 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,150 @@ + Branch work186, patch #64 + +Change TARGET_MODULO to TARGET_POWER9. + +This patch changes TARGET_MODULO to TARGET_POWER9. The -mmodulo switch is not +being changed, just the name of the macros used to determine if the PowerPC +processor supports ISA 3.0 (Power9). + +2024-11-15 Michael Meissner + +gcc/ + + * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): + Change TARGET_MODULO to TARGET_POWER9. + * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): + Likewise. + * gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise. + (TARGET_EXTSWSLI): Likewise. + (TARGET_MADDLD): Likewise. + (TARGET_POWER9): New macro. + * gcc/config/rs6000/rs6000.md (enabled attribute): Change TARGET_MODULO + to TARGET_POWER9. + (mod3): Likewise. + (umod3): Likewise. + (divide/modulo peephole2): Likewise. + + Branch work186, patch #63 + +Change TARGET_POPCNTD to TARGET_POWER7. + +This patch changes TARGET_POPCNTD to TARGET_POWER7. The -mpopcntd switch is not +being changed, just the name of the macros used to determine if the PowerPC +processor supports ISA 2.6 (Power7). + +2024-11-15 Michael Meissner + +gcc/ + + * gcc/config/rs6000/dfp.md (cmp_internal1): Change TARGET_POPCNTD + to TARGET_POWER7. + * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): + Likewise. + * gcc/config/rs6000/rs6000-string.cc (expand_block_compare): Likewise. + * gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): + Likewise. + (rs6000_option_override_internal): Likewise. + (rs6000_rtx_costs): Likewise. + * gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise. + (TARGET_FCFID): Likewise. + (TARGET_LFIWZX): Likewise. + (TARGET_FCFIDS): Likewise. + (TARGET_FCFIDU): Likewise. + (TARGET_FCFIDUS): Likewise. + (TARGET_FCTIDUZ): Likewise. + (TARGET_FCTIWUZ): Likewise. + (TARGET_FCTIDUZ): Likewise. + (TARGET_POWER7): New macro. + (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7. + (CTZ_DEFINED_VALUE_AT_ZERO): Likewise. + * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. + (lrintsi2): Likewise. + (lrintsi): Likewise. + (lrintsi_di): Likewise. + (cmpmemsi): Likewise. + (bpermd_): Likewise. + (addg6s): Likewise. + (cdtbcd): Likewise. + (cbcdtd): Likewise. + (div_): Likewise. + + Branch work186, patch #62 + +Change TARGET_CMPB to TARGET_POWER6. + +This patch changes TARGET_CMPB to TARGET_POWER6. The -mcmpb switch is not being +changed, just the name of the macros used to determine if the PowerPC processor +supports ISA 2.5 (Power6). + +2024-11-15 Michael Meissner + +gcc/ + + * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): + Change TARGET_CMPB to TARGET_POWER6. + * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): + Likewise. + (rs6000_rtx_costs): Likewise. + (rs6000_emit_parity): Likewise. + * gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise. + (TARGET_LFIWAX): Likewise. + (TARGET_POWER6): New macro. + (TARGET_EXTRA_BUILTINS): Change TARGET_CMPB to TARGET_POWER6. + * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. + (parity2_cmp): Likewise. + (cmpb3): Likewise. + (copysign3): Likewise. + (copysign3_fcpsgn): Likewise. + (cmpstrnsi): Likewise. + (cmpstrsi): Likewise. + + Branch work186, patch #61 + +Change TARGET_FPRND to TARGET_POWER5X. + +This patch changes TARGET_POWER5X to TARGET_POWER5. The -mfprnd switch is not +being changed, just the name of the macros used to determine if the PowerPC +processor supports ISA 2.4 (Power5x). + +2024-11-15 Michael Meissner + +gcc/ + + * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): + Change TARGET_FPRND to TARGET_POWER5X. + * gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro. + * gcc/config/rs6000/rs6000.md (fmod3): Change TARGET_FPRND to + TARGET_POWER5X. + (remainder3): Likewise. + (fctiwuz_): Likewise. + (ceil2): Likewise. + (floor2): Likewise. + (round2): Likewise. + +===
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:9d2bdd9137dfdd282eb4c9c60a6c8c582e97b198 commit 9d2bdd9137dfdd282eb4c9c60a6c8c582e97b198 Author: Michael Meissner Date: Fri Nov 15 12:06:21 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 20 1 file changed, 20 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index c16cb19021b7..e7f6c2a6d579 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,23 @@ + Branch work186, patch #53 + +Use vector pair load/store for memcpy with -mcpu=future + +In the development for the power10 processor, GCC did not enable using the load +vector pair and store vector pair instructions when optimizing things like +memory copy. This patch enables using those instructions if -mcpu=future is +used. + +2024-11-15 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable using + load vector pair and store vector pair instructions for memory copy + operations. + (POWERPC_MASKS): Make the bit for enabling using load vector pair and + store vector pair operations set and reset when the PowerPC processor is + changed. + Branch work186, patch #52 Add -mcpu=future tests.
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:69a0f14191878da0a9c23cd3c91068c0924096ca commit 69a0f14191878da0a9c23cd3c91068c0924096ca Author: Michael Meissner Date: Fri Nov 15 11:58:33 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 62 ++ 1 file changed, 62 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index e1d440886800..c16cb19021b7 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,65 @@ + Branch work186, patch #52 + +Add -mcpu=future tests. + +This patch adds simple tests for -mcpu=future. + +2024-11-15 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/future-1.c: New test. + * gcc.target/powerpc/future-2.c: Likewise. + + Branch work186, patch #51 + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-11-15 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work186, patch #50 + +Add support for -mcpu=future + +This patch adds the support that can be used in developing GCC support for +future PowerPC processors. + +2024-11-15 Michael Meissner + + * config.gcc (powerpc*-*-*): Add support for --with-cpu=future. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-arch.def: Add future cpu. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If + -mcpu=future, define _ARCH_FUTURE. + * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro. + (future cpu): Define. + * config/rs6000/rs6000-opts.h (enum processor_type): Add + PROCESSOR_FUTURE. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (power10_cost): Update comment. + (get_arch_flags): Add support for future processor. + (rs6000_option_override_internal): Likewise. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + (TARGET_POWER11): New macro. + * config/rs6000/rs6000.md (cpu attribute): Likewise. + Branch work186, patch #41 Use architecture flags for defining _ARCH_PWR macros.
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:c189f33bdc97c19028a2620bb29bf3d094f85bcb commit c189f33bdc97c19028a2620bb29bf3d094f85bcb Author: Michael Meissner Date: Fri Nov 15 11:40:18 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 123 + 1 file changed, 123 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 7085dc9802a7..e1d440886800 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,126 @@ + Branch work186, patch #41 + +Use architecture flags for defining _ARCH_PWR macros. + +For the newer architectures, this patch changes GCC to define the _ARCH_PWR +macros using the new architecture flags instead of relying on isa options like +-mpower10. + +The -mpower8-internal, -mpower10, and -mpower11 options were removed. The +-mpower11 option was removed completely, since it was just added in GCC 15. The +other two options were marked as WarnRemoved, and the various ISA bits were +removed. + +TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits +instead of the ISA bits. + +There are other internal isa bits that aren't removed with this patch because +the built-in function support uses those bits. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +Can I install this patch on the GCC 15 trunk? + +2024-11-15 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to + use architecture flags instead of ISA flags for setting most of the + _ARCH_PWR* macros. + (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call. + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove + OPTION_MASK_POWER8. + (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10. + (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11. + (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and + OPTION_MASK_POWER11. + * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update + declaration. + (rs6000_target_modify_macros_ptr): Likewise. + * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise. + (rs6000_option_override_internal): Use architecture flags instead of ISA + flags. + (rs6000_opt_masks): Remove -mpower10 and -mpower11, which are no longer + in the ISA flags. + (rs6000_pragma_target_parse): Use architecture flags as well as ISA + flags. + * config/rs6000/rs6000.h (TpARGET_POWER5): New macro. + (TARGET_POWER5X): Likewise. + (TARGET_POWER6): Likewise. + (TARGET_POWER7): Likewise. + (TARGET_POWER8): Likewise. + (TARGET_POWER9): Likewise. + (TARGET_POWER10): Likewise. + (TARGET_POWER11): Likewise. + * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits. + (-mpower10): Likewise. + (-mpower11): Likewise. + + Branch work186, patch #40 + +Add rs6000 architecture masks. + +This patch begins the journey to move architecture bits that are not user ISA +options from rs6000_isa_flags to a new targt variable rs6000_arch_flags. The +intention is to remove switches that are currently isa options, but the user +should not be using this particular option. For example, we want users to use +-mcpu=power10 and not just -mpower10. + +This patch also changes the target_clones support to use an architecture mask +instead of isa bits. + +This patch also switches the handling of .machine to use architecture masks if +they exist (power4 through power11). All of the other PowerPCs will continue to +use the existing code for setting the .machine option. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +In addition, I constructed a test case that used every archiecture define (like +_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran +this test for all supported combinations of -mcpu, big/little endian, and 32/64 +bit support. Every single instance generated exactly the same code with the +patches installed compared to the compiler before installing the patches. + +The only difference in this patch compared to the first version posted on +November 6th is that I the correct attribution and copyright year (i.e. that I +created rs6000-arch.def in 2024). + +Can I install this patch on the GCC 15 trunk? + +2024-11-15 Michael Meissner + +gcc/ + + * config/rs6000/default64.h (TARGET_CPU_DEFAULT): Set default cpu name. + * config/rs6000/rs6000-arch.def: New file. + * config/rs6000/rs6000.cc (struct clone_map): Switch to using + architecture masks instead of ISA masks. + (rs6000_clone_map): Likewise. + (rs6000_print_isa_options): Add an architecture flags argument, change + all callers. +
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:bd0913fd7db754c1a63baa34a2ecbda497d92de4 commit bd0913fd7db754c1a63baa34a2ecbda497d92de4 Author: Michael Meissner Date: Fri Nov 15 10:46:09 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 233 ++--- 1 file changed, 28 insertions(+), 205 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 842a7726a645..7085dc9802a7 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,53 +1,4 @@ - Branch work186, patch #21 - -Add -mcpu=future tuning support. - -This patch makes -mtune=future use the same tuning decision as -mtune=power11. - -2024-11-15 Michael Meissner - -gcc/ - - * config/rs6000/power10.md (all reservations): Add future as an - alterntive to power10 and power11. - - Branch work186, patch #20 - -Add support for -mcpu=future - -This patch adds the support that can be used in developing GCC support for -future PowerPC processors. - -2024-11-15 Michael Meissner - - * config.gcc (powerpc*-*-*): Add support for --with-cpu=future. - * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future. - * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. - * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. - * config/rs6000/driver-rs6000.cc (asm_names): Likewise. - * config/rs6000/rs6000-arch.def: Add future cpu. - * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If - -mcpu=future, define _ARCH_FUTURE. - * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro. - (future cpu): Define. - * config/rs6000/rs6000-opts.h (enum processor_type): Add - PROCESSOR_FUTURE. - * config/rs6000/rs6000-tables.opt: Regenerate. - * config/rs6000/rs6000.cc (power10_cost): Update comment. - (get_arch_flags): Add support for future processor. - (rs6000_option_override_internal): Likewise. - (rs6000_machine_from_flags): Likewise. - (rs6000_reassociation_width): Likewise. - (rs6000_adjust_cost): Likewise. - (rs6000_issue_rate): Likewise. - (rs6000_sched_reorder): Likewise. - (rs6000_sched_reorder2): Likewise. - (rs6000_register_move_cost): Likewise. - * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. - (TARGET_POWER11): New macro. - * config/rs6000/rs6000.md (cpu attribute): Likewise. - - Branch work186, patch #12 + Branch work186, patch #35 Do not allow -mvsx to boost processor to power7. @@ -59,13 +10,8 @@ support, it will be an error. I have built both big endian and little endian bootstrap compilers and there were no regressions. -In addition, I constructed a test case that used every archiecture define (like -_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran -this test for all supported combinations of -mcpu, big/little endian, and 32/64 -bit support. Every single instance generated exactly the same code with the -patches installed compared to the compiler before installing the patches. - -I updated the 2 tests that used -mvsx to raise the cpu to power7. +I updated the 2 tests that used -mvsx to raise the cpu to power7, and the test +case that checks if -mno-vsx produces the expected warning. Can I install this patch on the GCC 15 trunk? @@ -73,146 +19,20 @@ Can I install this patch on the GCC 15 trunk? gcc/ - * config/rs6000/rs6000.cc (report_architecture_mismatch): New function. - Report an error if the user used an option such as -mvsx when the - default processor would not allow the option. - (rs6000_option_override_internal): Move some ISA checking code into - report_architecture_mismatch. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Check if + the user asked for VSX instructions whether the cpu was at least power7. gcc/testsuite/ * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7 when we need to add VSX support. Add test for adding cpu=power7 no-vsx to generate only Altivec instructions. - * gcc.target/powerpc/pr115688.c: Add -mdejagnu-cpu=power6 when - requesting VSX instructions. - * gcc.target/powerpc/pr87496-1.c: Update optins to use + * gcc.target/powerpc/pr115688.c: Add cpu=power7 in target __attribute__ + when requesting VSX instructions. + * gcc.target/powerpc/pr87496-1.c: Update options to use -mdejagnu-cpu=power6 to get the appropriate error message. - Branch work186, patch #11 - -Use architecture flags for defining _ARCH_PWR macros. - -For the newer architectures, this patch changes GCC to define the _ARCH_PWR -macros using the new architecture flags instead of relying on isa options li
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:81b2cdf680f510a230b88c8f86e1caffb9ef71cd commit 81b2cdf680f510a230b88c8f86e1caffb9ef71cd Author: Michael Meissner Date: Fri Nov 15 00:57:55 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index b119fcae6a40..842a7726a645 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -84,8 +84,10 @@ gcc/testsuite/ * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7 when we need to add VSX support. Add test for adding cpu=power7 no-vsx to generate only Altivec instructions. - * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX - instructions. + * gcc.target/powerpc/pr115688.c: Add -mdejagnu-cpu=power6 when + requesting VSX instructions. + * gcc.target/powerpc/pr87496-1.c: Update optins to use + -mdejagnu-cpu=power6 to get the appropriate error message. Branch work186, patch #11
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:f79eae4896f752e695fe555c911791da5cb9bec1 commit f79eae4896f752e695fe555c911791da5cb9bec1 Author: Michael Meissner Date: Thu Nov 14 23:47:43 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 20 +--- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 4c21bfdabe10..b119fcae6a40 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -4,7 +4,7 @@ Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. -2024-11-14 Michael Meissner +2024-11-15 Michael Meissner gcc/ @@ -18,7 +18,7 @@ Add support for -mcpu=future This patch adds the support that can be used in developing GCC support for future PowerPC processors. -2024-11-14 Michael Meissner +2024-11-15 Michael Meissner * config.gcc (powerpc*-*-*): Add support for --with-cpu=future. * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future. @@ -69,7 +69,7 @@ I updated the 2 tests that used -mvsx to raise the cpu to power7. Can I install this patch on the GCC 15 trunk? -2024-11-14 Michael Meissner +2024-11-15 Michael Meissner gcc/ @@ -79,8 +79,6 @@ gcc/ (rs6000_option_override_internal): Move some ISA checking code into report_architecture_mismatch. -2024-11-06 Michael Meissner - gcc/testsuite/ * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7 @@ -113,7 +111,7 @@ were no regressions. Can I install this patch on the GCC 15 trunk? -2024-11-14 Michael Meissner +2024-11-15 Michael Meissner gcc/ @@ -220,7 +218,7 @@ This patch changes TARGET_MODULO to TARGET_POWER9. The -mmodulo switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 3.0 (Power9). -2024-11-14 Michael Meissner +2024-11-15 Michael Meissner gcc/ @@ -246,7 +244,7 @@ This patch changes TARGET_POPCNTD to TARGET_POWER7. The -mpopcntd switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.6 (Power7). -2024-11-14 Michael Meissner +2024-11-15 Michael Meissner gcc/ @@ -293,7 +291,7 @@ This patch changes TARGET_CMPB to TARGET_POWER6. The -mcmpb switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.5 (Power6). -2024-11-14 Michael Meissner +2024-11-15 Michael Meissner gcc/ @@ -324,7 +322,7 @@ This patch changes TARGET_POWER5X to TARGET_POWER5. The -mfprnd switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.4 (Power5x). -2024-11-14 Michael Meissner +2024-11-15 Michael Meissner gcc/ @@ -348,7 +346,7 @@ This patch changes TARGET_POPCNTB to TARGET_POWER5. The -mpopcntb switch is not being changed in this patch, just the name of the macros used to determine if the PowerPC processor supports ISA 2.2 (Power5). -2024-11-14 Michael Meissner +2024-11-15 Michael Meissner gcc/
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:8c6b674e36d5918fda788bb26b5bceb1bdb484f2 commit 8c6b674e36d5918fda788bb26b5bceb1bdb484f2 Author: Michael Meissner Date: Thu Nov 14 23:44:04 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 214 + 1 file changed, 214 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 23f7f779b59c..4c21bfdabe10 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,217 @@ + Branch work186, patch #21 + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-11-14 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work186, patch #20 + +Add support for -mcpu=future + +This patch adds the support that can be used in developing GCC support for +future PowerPC processors. + +2024-11-14 Michael Meissner + + * config.gcc (powerpc*-*-*): Add support for --with-cpu=future. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-arch.def: Add future cpu. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If + -mcpu=future, define _ARCH_FUTURE. + * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro. + (future cpu): Define. + * config/rs6000/rs6000-opts.h (enum processor_type): Add + PROCESSOR_FUTURE. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (power10_cost): Update comment. + (get_arch_flags): Add support for future processor. + (rs6000_option_override_internal): Likewise. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + (TARGET_POWER11): New macro. + * config/rs6000/rs6000.md (cpu attribute): Likewise. + + Branch work186, patch #12 + +Do not allow -mvsx to boost processor to power7. + +This patch restructures the code so that -mvsx for example will not silently +convert the processor to power7. The user must now use -mcpu=power7 or higher. +This means if the user does -mvsx and the default processor does not have VSX +support, it will be an error. + +I have built both big endian and little endian bootstrap compilers and there +were no regressions. + +In addition, I constructed a test case that used every archiecture define (like +_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran +this test for all supported combinations of -mcpu, big/little endian, and 32/64 +bit support. Every single instance generated exactly the same code with the +patches installed compared to the compiler before installing the patches. + +I updated the 2 tests that used -mvsx to raise the cpu to power7. + +Can I install this patch on the GCC 15 trunk? + +2024-11-14 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (report_architecture_mismatch): New function. + Report an error if the user used an option such as -mvsx when the + default processor would not allow the option. + (rs6000_option_override_internal): Move some ISA checking code into + report_architecture_mismatch. + +2024-11-06 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7 + when we need to add VSX support. Add test for adding cpu=power7 no-vsx + to generate only Altivec instructions. + * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX + instructions. + + Branch work186, patch #11 + +Use architecture flags for defining _ARCH_PWR macros. + +For the newer architectures, this patch changes GCC to define the _ARCH_PWR +macros using the new architecture flags instead of relying on isa options like +-mpower10. + +The -mpower8-internal, -mpower10, and -mpower11 options were removed. The +-mpower11 option was removed completely, since it was just added in GCC 15. The +other two options were marked as WarnRemoved, and the various ISA bits were +removed. + +TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits +instead of the ISA bits. + +There are other internal isa bits that aren't removed with this patch because +the built-in function support uses thos
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:67e4c2848c8fce5874286ebaf3b53c50bc9e8793 commit 67e4c2848c8fce5874286ebaf3b53c50bc9e8793 Author: Michael Meissner Date: Thu Nov 14 23:04:02 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 137 + 1 file changed, 46 insertions(+), 91 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index c1b29fd68f37..23f7f779b59c 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -2,58 +2,50 @@ Change TARGET_MODULO to TARGET_POWER9. -This patch changes TARGET_MODULO to TARGET_POWER9 and OPTION_MASK_MODULO to -OPTION_MASK_POWER9. The -mmodulo switch is not being changed, just the name of -the macros used to determine if the PowerPC processor supports ISA 3.0 (Power9). +This patch changes TARGET_MODULO to TARGET_POWER9. The -mmodulo switch is not +being changed, just the name of the macros used to determine if the PowerPC +processor supports ISA 3.0 (Power9). 2024-11-14 Michael Meissner gcc/ * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): - Change TARGET_MODULO to TARGET_POWER9. Change OPTION_MASK_MODULO to - OPTION_MASK_POWER9. - * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise. - * gcc/config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Likewise. - (POWERPC_MASKS): Likewise. + Change TARGET_MODULO to TARGET_POWER9. * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. - (rs6000_opt_masks): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise. (TARGET_EXTSWSLI): Likewise. (TARGET_MADDLD): Likewise. - * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. + (TARGET_POWER9): New macro. + * gcc/config/rs6000/rs6000.md (enabled attribute): Change TARGET_MODULO + to TARGET_POWER9. (mod3): Likewise. (umod3): Likewise. (divide/modulo peephole2): Likewise. - * gcc/config/rs6000/rs6000.opt (-mmodulo): Likewise. Branch work186, patch #4 Change TARGET_POPCNTD to TARGET_POWER7. -This patch changes TARGET_POPCNTD to TARGET_POWER7 and OPTION_MASK_POPCNTD to -OPTION_MASK_POWER7. The -mpopcntd switch is not being changed, just the name of -the macros used to determine if the PowerPC processor supports ISA 2.6 (Power7). +This patch changes TARGET_POPCNTD to TARGET_POWER7. The -mpopcntd switch is not +being changed, just the name of the macros used to determine if the PowerPC +processor supports ISA 2.6 (Power7). 2024-11-14 Michael Meissner gcc/ * gcc/config/rs6000/dfp.md (cmp_internal1): Change TARGET_POPCNTD - to TARGET_POWER7. Change OPTION_MASK_POPCNTD to OPTION_MASK_POWER7. + to TARGET_POWER7. * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Likewise. - * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise. - * gcc/config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_EMBEDDED): Likewise. - (ISA_2_6_MASKS_SERVER): Likewise. - (POWERPC_MASKS): Likewise. * gcc/config/rs6000/rs6000-string.cc (expand_block_compare): Likewise. - * gcc/config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise. - (rs6000_hard_regno_mode_ok_uncached): Likewise. + * gcc/config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): + Likewise. (rs6000_option_override_internal): Likewise. (rs6000_rtx_costs): Likewise. - (rs6000_opt_masks): Likewise. + (rs6000_emit_popcount): Likewise. * gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise. (TARGET_FCFID): Likewise. (TARGET_LFIWZX): Likewise. @@ -63,13 +55,13 @@ gcc/ (TARGET_FCTIDUZ): Likewise. (TARGET_FCTIWUZ): Likewise. (TARGET_FCTIDUZ): Likewise. - (TARGET_EXTRA_BUILTINS): Likewise. + (TARGET_POWER7): New macro. + (TARGET_EXTRA_BUILTINS): Change TARGET_POPCNTD to TARGET_POWER7. (CTZ_DEFINED_VALUE_AT_ZERO): Likewise. * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. (ctz2): Likewise. - (ffs2): Likewise. - (popcntb2): Likewise. - (lrintsi): Likewise. + (popcntd2): Likewise. + (lrintsi2): Likewise. (lrintsi): Likewise. (lrintsi_di): Likewise. (cmpmemsi): Likewise. @@ -78,125 +70,88 @@ gcc/ (cdtbcd): Likewise. (cbcdtd): Likewise. (div_): Likewise. - * gcc/config/rs6000/rs6000.opt (-mpopcntd): Likewise. Branch work186, patch #3 Change TARGET_CMPB to TARGET_POWER6. -This patch changes TARGET_CMPB to TARGET_POWER6 and OPTION_MASK_CMPB to -OPTION_MASK_POWER6. The -mcmpb switch is not being changed, just the name of -the macros used to determine if the PowerPC processor supports ISA 2.5 (Power6). +This p
[gcc(refs/users/meissner/heads/work186)] Update ChangeLog.*
https://gcc.gnu.org/g:578f73b983bf04e1ee7724548e298ad4487bdd22 commit 578f73b983bf04e1ee7724548e298ad4487bdd22 Author: Michael Meissner Date: Thu Nov 14 14:50:10 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 233 + 1 file changed, 233 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 81b644bdeb4f..c1b29fd68f37 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,5 +1,238 @@ + Branch work186, patch #5 + +Change TARGET_MODULO to TARGET_POWER9. + +This patch changes TARGET_MODULO to TARGET_POWER9 and OPTION_MASK_MODULO to +OPTION_MASK_POWER9. The -mmodulo switch is not being changed, just the name of +the macros used to determine if the PowerPC processor supports ISA 3.0 (Power9). + +2024-11-14 Michael Meissner + +gcc/ + + * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): + Change TARGET_MODULO to TARGET_POWER9. Change OPTION_MASK_MODULO to + OPTION_MASK_POWER9. + * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise. + * gcc/config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Likewise. + (POWERPC_MASKS): Likewise. + * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): + Likewise. + (rs6000_opt_masks): Likewise. + * gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise. + (TARGET_EXTSWSLI): Likewise. + (TARGET_MADDLD): Likewise. + * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. + (mod3): Likewise. + (umod3): Likewise. + (divide/modulo peephole2): Likewise. + * gcc/config/rs6000/rs6000.opt (-mmodulo): Likewise. + + Branch work186, patch #4 + +Change TARGET_POPCNTD to TARGET_POWER7. + +This patch changes TARGET_POPCNTD to TARGET_POWER7 and OPTION_MASK_POPCNTD to +OPTION_MASK_POWER7. The -mpopcntd switch is not being changed, just the name of +the macros used to determine if the PowerPC processor supports ISA 2.6 (Power7). + +2024-11-14 Michael Meissner + +gcc/ + + * gcc/config/rs6000/dfp.md (cmp_internal1): Change TARGET_POPCNTD + to TARGET_POWER7. Change OPTION_MASK_POPCNTD to OPTION_MASK_POWER7. + * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): + Likewise. + * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise. + * gcc/config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_EMBEDDED): Likewise. + (ISA_2_6_MASKS_SERVER): Likewise. + (POWERPC_MASKS): Likewise. + * gcc/config/rs6000/rs6000-string.cc (expand_block_compare): Likewise. + * gcc/config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_option_override_internal): Likewise. + (rs6000_rtx_costs): Likewise. + (rs6000_opt_masks): Likewise. + * gcc/config/rs6000/rs6000.h (TARGET_LDBRX): Likewise. + (TARGET_FCFID): Likewise. + (TARGET_LFIWZX): Likewise. + (TARGET_FCFIDS): Likewise. + (TARGET_FCFIDU): Likewise. + (TARGET_FCFIDUS): Likewise. + (TARGET_FCTIDUZ): Likewise. + (TARGET_FCTIWUZ): Likewise. + (TARGET_FCTIDUZ): Likewise. + (TARGET_EXTRA_BUILTINS): Likewise. + (CTZ_DEFINED_VALUE_AT_ZERO): Likewise. + * gcc/config/rs6000/rs6000.md (enabled attribute): Likewise. + (ctz2): Likewise. + (ffs2): Likewise. + (popcntb2): Likewise. + (lrintsi): Likewise. + (lrintsi): Likewise. + (lrintsi_di): Likewise. + (cmpmemsi): Likewise. + (bpermd_): Likewise. + (addg6s): Likewise. + (cdtbcd): Likewise. + (cbcdtd): Likewise. + (div_): Likewise. + * gcc/config/rs6000/rs6000.opt (-mpopcntd): Likewise. + + Branch work186, patch #3 + +Change TARGET_CMPB to TARGET_POWER6. + +This patch changes TARGET_CMPB to TARGET_POWER6 and OPTION_MASK_CMPB to +OPTION_MASK_POWER6. The -mcmpb switch is not being changed, just the name of +the macros used to determine if the PowerPC processor supports ISA 2.5 (Power6). + +2024-11-14 Michael Meissner + +gcc/ + + * gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): + Change TARGET_CMPB to TARGET_POWER6. Change OPTION_MASK_CMPB to + OPTION_MASK_POWER6. + * gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise. + * gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): Likewise. + (POWERPC_MASKS): Likewise. + (476 cpu definition): Likewise. + (476fp cpu definition): Likewise. + (a2 cpu definition): Likewise. + (power6 cpu definition): Likewise. + * gcc/config/rs6000/rs6000.cc (rs6000_clone_map): Likewise. + (rs6000_option_override_internal): Likewise. + (rs6000_rtx_costs): Likewise. + (rs6000
