[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2026-01-29 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:513d446d84f99e30f377b0479e148284ff4c4a9d

commit 513d446d84f99e30f377b0479e148284ff4c4a9d
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2026-01-16 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:e27f8f83f9959f4db5f50a2fbbd8ad9c6c8e6257

commit e27f8f83f9959f4db5f50a2fbbd8ad9c6c8e6257
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2025-11-07 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:8c1eceff4000ffe51561abddcd946e576c55657e

commit 8c1eceff4000ffe51561abddcd946e576c55657e
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2025-11-01 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:d0984167c7aca60d216b846fe6f334df316376df

commit d0984167c7aca60d216b846fe6f334df316376df
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2025-10-18 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:30e7e3e8844a856a9799d02b59060a70a4b24181

commit 30e7e3e8844a856a9799d02b59060a70a4b24181
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2025-09-13 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:7854069c14a4ae986654576dd3e11617256fa7fa

commit 7854069c14a4ae986654576dd3e11617256fa7fa
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2025-09-06 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:94b41ed01f858cf424de65f7b5a7263609024e0c

commit 94b41ed01f858cf424de65f7b5a7263609024e0c
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2025-08-25 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:1a4622c5209342ce4062df58e51c20b28b271cdc

commit 1a4622c5209342ce4062df58e51c20b28b271cdc
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2025-07-23 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:cd7a4523dd963d56d04110e289dee124feb59e44

commit cd7a4523dd963d56d04110e289dee124feb59e44
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2025-07-05 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:c36c104eb5f27a3f5343f3c06d07252db8b793e1

commit c36c104eb5f27a3f5343f3c06d07252db8b793e1
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new operand constraint: cR

2025-05-19 Thread Jeff Law via Gcc-cvs 
https://gcc.gnu.org/g:fd457d64ad74643e5bab355aefc28ef68a071a58

commit fd457d64ad74643e5bab355aefc28ef68a071a58
Author: Kito Cheng 
Date:   Mon May 12 14:36:07 2025 +0800

RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose 
register
(x8-x15) in inline asm.

Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102

gcc/ChangeLog:

* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/constraint-cR-pair.c: New test case.

(cherry picked from commit c9eb473fb9946f642506d24f4131d7c83855fd78)

Diff:
---
 gcc/config/riscv/constraints.md |  4 
 gcc/doc/md.texi |  3 +++
 gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c | 13 +
 3 files changed, 20 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 18556a591411..58355cf03f2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -43,6 +43,10 @@
 (define_register_constraint "cf" "TARGET_HARD_FLOAT ? RVC_FP_REGS : 
(TARGET_ZFINX ? RVC_GR_REGS : NO_REGS)"
   "RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when 
use zfinx.")
 
+(define_register_constraint "cR" "RVC_GR_REGS"
+  "Even-odd RVC general purpose register (x8-x15)."
+  "regno % 2 == 0")
+
 ;; General constraints
 
 (define_constraint "I"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ae7a6017a25e..cdf99cb79798 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3703,6 +3703,9 @@ RVC general purpose register (x8-x15).
 RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use
 zfinx.
 
+@item cR
+Even-odd RVC general purpose register pair.
+
 @item R
 Even-odd general purpose register pair.
 
diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c 
b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
new file mode 100644
index ..479246b632a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int 
m0, int m1) {
+/*
+** foo:
+**   ...
+**   addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0)
+**   ...
+*/
+__asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory");
+}