On 26 March 2014 15:45, Jakub Jelinek ja...@redhat.com wrote:
On Wed, Mar 26, 2014 at 03:30:44PM +0800, Zhenqiang Chen wrote:
Agree. CSE should never modify asm insns to drop some of the outputs.
So the right fix is top prevent this from happening, not papering over about
it.
But in this
Hello,
Straightforward patch in the bottom fixes
copy-and-paste problem in initialization part
of tests.
Updated tests pass on simulator.
Is it ok for trunk?
gcc/testsuite:
* gcc.target/i386/avx512f-vshuff32x4-2.c: Fix initialization
of second source operand.
*
On Thu, Mar 27, 2014 at 10:18 AM, Kirill Yukhin kirill.yuk...@gmail.com wrote:
Straightforward patch in the bottom fixes
copy-and-paste problem in initialization part
of tests.
Updated tests pass on simulator.
Is it ok for trunk?
gcc/testsuite:
*
Adding Balaji.
--Alexander
2014-03-26 18:56 GMT+04:00 Alexander Ivchenko aivch...@gmail.com:
Hi,
In gcc/config/linux-android.h we have builtin_define (__ANDROID__);
So ANDROID as in libcilkrts now is not the correct macro to check.
Bootstrapped and passed cilk testsuite on
Hello Ulrich,
On 21 Mar 06:41, Ulrich Drepper wrote:
From personal experience I find it
very frustrating if a gcc release doesn't have the complete set of
intrinsics since then you have to provide your own implementations in
code which doesn't assume the latest compiler.
I think I should
Hi,
AArch64 zip_* intrinsics are currently implemented with temporary inline asm,
which prevent analysis through themselves. This is to replace those asm blocks
with (equivalent) calls to __builtin_shuffle, which produce the same assembler
instructions (unless gcc can do better).
First
This patch replaces the temporary inline assembler for vzip_* in arm_neon.h with
equivalent calls to __builtin_shuffle. These are matched by
aarch64_expand_vec_perm_const{,_1} to output the same assembler instructions.
Tests from first patch still passing on aarch64-none-elf and
This adds DejaGNU tests of the existing AArch64 vzip_* intrinsics, both checking
the assembler output and the runtime results. Test bodies are in separate files
ready to reuse for ARM in the third patch. Putting these in a new subdirectory
ready for tests of other/related intrinsics.
All
Final patch adds new tests of the ARM ZIP Intrinsics (subsuming the
autogenerated ones in testsuite/gcc.target/arm/neon/), that also check the
execution results, reusing the test bodies introduced into AArch64 in the first
patch.
All tests passing on arm-none-eabi.
gcc/testsuite/ChangeLog:
-Original Message-
From: Richard Earnshaw
Sent: 21 March 2014 13:57
To: Ian Bolton
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH, ARM] Optimise NotDI AND/OR ZeroExtendSI for ARMv7A
On 19/03/14 16:53, Ian Bolton wrote:
This is a follow-on patch to one already committed:
-O0 (test for excess errors)
Excess errors:
/usr/local/gcc/gcc-20140327/gcc/testsuite/g++.dg/torture/pr60315.C:7:19:
warning: override controls (override/final) only available with -std=c++11 or
-std=gnu++11
/usr/local/gcc/gcc-20140327/gcc/testsuite/g++.dg/torture/pr60315.C:7:21:
warning
Jason Merrill ja...@redhat.com writes:
diff --git a/gcc/testsuite/g++.dg/abi/thunk6.C
b/gcc/testsuite/g++.dg/abi/thunk6.C
new file mode 100644
index 000..e3d07f2
--- /dev/null
+++ b/gcc/testsuite/g++.dg/abi/thunk6.C
@@ -0,0 +1,18 @@
+// PR c++/60566
+// We need to emit the
Hi,
This is a partial fix for PR60655 where dwarf2out.c rejects NOT of a
value in const_ok_for_output_1. There is still a problem with the
testcase on armhf where we get operations of the form, const (minus
(const_int) (symref)) without the -fdata-sections option which is just
weird. I'm
* include/bits/ios_base.h (hexfloat): New function.
(defaultfloat): New function.
* src/c++98/locale_facets.cc (__num_base::_S_format_float):
Support hexadecimal floating point format.
* testsuite/27_io/basic_ostream/inserters_arithmetic/char/hexfloat.cc:
New file.
hexfloat/defaultfloat are new
On 24-Mar-14, at 2:45 AM, Rainer Orth wrote:
John David Anglin dave.ang...@bell.net writes:
Index: gcc.dg/torture/pr60092.c
===
--- gcc.dg/torture/pr60092.c(revision 208769)
+++ gcc.dg/torture/pr60092.c(working copy)
@@
On Wed, 26 Mar 2014 10:25:19 -0600
Tom Tromey tro...@redhat.com wrote:
Julian == Julian Brown jul...@codesourcery.com writes:
Julian include/
Julian * dwarf2.h (enum dwarf_calling_convention): Add
Julian DW_CC_GNU_thiscall_i386.
We've been trying to ensure that all GNU DWARF
Hi!
gimplify_regimplify_operands doesn't grok gimple_clobber_p stmts
very well (tries to regimplify the CONSTRUCTOR), but in the only case
where we might need to regimplify them in omp-low.c (the addressable
local vars in simd regions, remember this is before inlining) the clobbers
actually don't
+#ifdef ACCEL_COMPILER
+ /* Decls are placed in reversed order in fat-objects, so we need to
+ revert them back if we compile target. */
...
Actually this change is incorrect. If host binary is built with -flto, then
both host gcc and target gcc read decls from lto and target_lto sections
On 27/03/14 12:52 +0100, Rüdiger Sonderfeld wrote:
* include/bits/ios_base.h (hexfloat): New function.
(defaultfloat): New function.
* src/c++98/locale_facets.cc (__num_base::_S_format_float):
Support hexadecimal floating point format.
*
On 03/27/2014 02:31 PM, Ilya Verbin wrote:
+#ifdef ACCEL_COMPILER
+ /* Decls are placed in reversed order in fat-objects, so we need to
+ revert them back if we compile target. */
...
Actually this change is incorrect. If host binary is built with -flto, then
both host gcc and target
On 03/27/2014 02:31 PM, Ilya Verbin wrote:
+#ifdef ACCEL_COMPILER
+ /* Decls are placed in reversed order in fat-objects, so we need to
+ revert them back if we compile target. */
...
Actually this change is incorrect. If host binary is built with -flto, then
both host gcc and target
On Wed, Mar 26, 2014 at 09:53:47PM +, Richard Sandiford wrote:
Richard Henderson r...@redhat.com writes:
On 03/26/2014 12:40 PM, Jakub Jelinek wrote:
On Wed, Mar 26, 2014 at 01:32:44PM -0600, Jeff Law wrote:
On 03/26/14 12:28, Jakub Jelinek wrote:
(mult:SI (const_int 0) (const_int 4))
Hi,
with r207507 I've made our fp to int conversion routines available
also for the 32 bit biarch libgcc. The patch included these also for
the 64 bit libgcc which is wrong since it prevent routines like
fixsfti from being generated by libgcc2.c.
The attached patch fixes the following testsuite
On Thu, Mar 27, 2014 at 05:31:29PM +0400, Ilya Verbin wrote:
+#ifdef ACCEL_COMPILER
+ /* Decls are placed in reversed order in fat-objects, so we need to
+ revert them back if we compile target. */
...
Actually this change is incorrect. If host binary is built with -flto, then
both
On Thu, Mar 27, 2014 at 02:59:05PM +0100, Andreas Krebbel wrote:
Hi,
with r207507 I've made our fp to int conversion routines available
also for the 32 bit biarch libgcc. The patch included these also for
the 64 bit libgcc which is wrong since it prevent routines like
fixsfti from being
On 03/27/2014 06:51 AM, Jakub Jelinek wrote:
Did you mean Jeff's original change, or say:
--- gcc/config/i386/i386.c2014-03-20 17:41:45.917689676 +0100
+++ gcc/config/i386/i386.c2014-03-27 14:47:21.876254288 +0100
@@ -13925,13 +13925,13 @@ ix86_legitimize_address (rtx x, rtx oldx
Actually I suppose this is obvious enough, so will commit it today.
On Tue, Mar 25, 2014 at 09:59:39PM +0100, Marek Polacek wrote:
ffs builtins had wrong type of parameters.
2014-03-25 Marek Polacek pola...@redhat.com
PR c/50347
* doc/extend.texi (ffs Builtins): Change
On 27/03/14 15:15, Jakub Jelinek wrote:
Does this fix the:
-__fixdfti@@GCC_3.0 FUNC GLOBAL DEFAULT
-__fixsfti@@GCC_3.0 FUNC GLOBAL DEFAULT
-__fixtfti@@GCC_4.1.0 FUNC GLOBAL DEFAULT
-__fixunsdfti@@GCC_3.0 FUNC GLOBAL DEFAULT
-__fixunssfti@@GCC_3.0 FUNC GLOBAL DEFAULT
-__fixunstfti@@GCC_4.1.0
On 03/26/14 15:53, Richard Sandiford wrote:
Richard Henderson r...@redhat.com writes:
On 03/26/2014 12:40 PM, Jakub Jelinek wrote:
On Wed, Mar 26, 2014 at 01:32:44PM -0600, Jeff Law wrote:
On 03/26/14 12:28, Jakub Jelinek wrote:
(mult:SI (const_int 0) (const_int 4)) is IMHO far from being
On Wed, Mar 26, 2014 at 08:30:39PM -0400, David Edelsohn wrote:
Okay.
Good to add the optimizations.
I notice that you emit nop with a comment after a # character. I
notice that you also added that to the POWER8 vector fusion peepholes.
Is it safe to assume that all assemblers for
On Thu, Mar 27, 2014 at 04:32:19PM +0100, Andreas Krebbel wrote:
On 27/03/14 15:15, Jakub Jelinek wrote:
Does this fix the:
-__fixdfti@@GCC_3.0 FUNC GLOBAL DEFAULT
-__fixsfti@@GCC_3.0 FUNC GLOBAL DEFAULT
-__fixtfti@@GCC_4.1.0 FUNC GLOBAL DEFAULT
-__fixunsdfti@@GCC_3.0 FUNC GLOBAL
Hello Jonathan,
thanks for your comments.
N.B. patches to the ChangeLog rarely apply cleanly (because someone
else may have changed the ChangeLog since the patch was created) so
the convention is to send the ChangeLog entry in the email body, or as
a separate attachment, or by using 'git log
On Wed, Mar 26, 2014 at 4:05 PM, Xinliang David Li davi...@google.com wrote:
is cgraph_init_gid_map called after linking?
Oh, forgot that part. It's interesting that the test can pass without
another cgraph_init_gid_map call.
Patch updated. Retested and the performance is OK.
Dehao
David
On 27 Mar 15:02, Jakub Jelinek wrote:
The tables need to be created before IPA, that way it really shouldn't
matter in what order you emit them. E.g. the outlined target functions
could be added to the table during ompexp pass which actually creates the
outlined functions, the vars need to be
On 03/27/14 07:51, Jakub Jelinek wrote:
On Wed, Mar 26, 2014 at 09:53:47PM +, Richard Sandiford wrote:
Richard Henderson r...@redhat.com writes:
On 03/26/2014 12:40 PM, Jakub Jelinek wrote:
On Wed, Mar 26, 2014 at 01:32:44PM -0600, Jeff Law wrote:
On 03/26/14 12:28, Jakub Jelinek wrote:
On Thu, Mar 27, 2014 at 10:17:26AM -0600, Jeff Law wrote:
Did you mean Jeff's original change, or say:
--- gcc/config/i386/i386.c 2014-03-20 17:41:45.917689676 +0100
+++ gcc/config/i386/i386.c 2014-03-27 14:47:21.876254288 +0100
@@ -13925,13 +13925,13 @@ ix86_legitimize_address (rtx x, rtx
On 03/27/2014 01:42 AM, Jan Hubicka wrote:
I belive the problem here is the _vptr.MultiTermDocs vtable is initialized from
VTT that is not understood by ipa-prop jump functions.
Makes sense. It would be good to update those functions to understand
that the initialization is always setting
On 27/03/14 17:00 +0100, Rüdiger Sonderfeld wrote:
Hello Jonathan,
thanks for your comments.
N.B. patches to the ChangeLog rarely apply cleanly (because someone
else may have changed the ChangeLog since the patch was created) so
the convention is to send the ChangeLog entry in the email body,
On 03/26/2014 09:12 PM, Adam Butcher wrote:
+Note: cp_binding_level::class_shadowed is used as a predicate to
+indicate whether a class scope is a class-defining scope. We stop
+at the first such scope as this will be the currently open class
+
Hi,
Much like the zip intrinsics, the vuzp_* intrinsics are implemented with inline
ASM, which prevents compiler analysis. This series replaces those with calls to
_builtin_shuffle, which produce the same** assembler instructions.
(**except for two-element vectors where UZP and ZIP are
This adds DejaGNU tests of the existing AArch64 vuzp_* intrinsics, both checking
the assembler output and the runtime results. Test bodies are in separate files
ready to reuse for ARM in the third patch.
Putting these in a new subdirectory with the ZIP Intrinsic tests, using simd.exp
added
This patch replaces the temporary inline assembler for vuzp_* in arm_neon.h with
equivalent calls to __builtin_shuffle. These are matched by
aarch64_expand_vec_perm_const{,_1} to output (generally) the same assembler
instructions. That is, except for two-element vectors, where ZIP, UZP and
inal patch in series, adds new tests of the ARM UZP Intrinsics (subsuming the
autogenerated ones in testsuite/gcc.target/arm/neon/), that also check the
execution results, reusing the test bodies introduced into AArch64 in the first
patch.
Tests use gcc.target/arm/simd/simd.exp from
Hi,
The rtx_costs implementation in the ARM backend dumps the partial
or total computed cost of an insn as it goes along. This
functionality proves useful when debugging aarch64_rtx_costs,
so we should port it across.
Tested on aarch64-none-elf in series with no issues.
OK for stage 1?
Hi,
This patch wires up the address and vector cost tables for the
Cortex-A57 processor.
Tested on aarch64-none-elf.
OK for stage 1?
Thanks,
James
---
2014-03-27 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64.c (cortexa57_addrcost_table): New.
Hi,
The address cost function, as it stands, is fairly limited.
Rather than write a lot of new walking code, we would instead
like to reuse some of the existing infrastructure which can
categorize an address.
This patch therefore rewires aarch64_address_costs to use
aarch64_classify_address,
Hi,
Next, comparisons, flag setting operations and IF_THEN_ELSE.
Tested on aarch64-none-elf.
Ok for stage 1?
Thanks,
James
---
2014-03-27 James Greenhalgh james.greenha...@arm.com
Philipp Tomsich philipp.toms...@theobroma-systems.com
* config/aarch64/aarch64.c
Hi,
One thing we might want to be more accurate in costing is building
an integer from scratch.
To estimate this, we can repurpose aarch64_build_constant. If we
take an additional flag to decide whether we should actually emit
instructions, we can simply count the number of instructions we
Hi,
Next SIGN_EXTRACT/ZERO_EXTRACT.
Tested in series on aarch64-none-elf.
OK for stage 1?
Thanks,
James
---
2014-03-27 James Greenhalgh james.greenha...@arm.com
Philipp Tomsich philipp.toms...@theobroma-systems.com
* config/aarch64/aarch64.c (aarch64_rtx_costs):
Hi,
Now DIV/MOD.
Tested in series on aarch64-none-elf.
OK for stage 1?
Thanks,
James
---
2014-03-27 James Greenhalgh james.greenha...@arm.com
Philipp Tomsich philipp.toms...@theobroma-systems.com
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
Hi,
Next, costs for SYMBOL_REF, HIGH and LO_SUM.
Tested in series on aarch64-none-elf.
OK for Stage-1?
Thanks,
James
---
2014-03-27 James Greenhalgh james.greenha...@arm.com
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost SYMBOL_REF,
HIGH, LO_SUM.
diff --git
Hi,
Next up are costs for the logical operations (AND, OR, etc.).
Tested in series for aarch64-none-elf.
OK for stage 1?
Thanks,
James
---
2014-03-27 James Greenhalgh james.greenha...@arm.com
Philipp Tomsich philipp.toms...@theobroma-systems.com
*
Hi,
This patch adds functionality for costing a SET RTX.
Often these are free in the sense that we factor the cost of the set
in to the cost of the RHS of the insn. Notable exceptions are sets to
MEM which should be costed as a store, and simple register moves, which
should be costed.
Tested
Hi,
The GCC rtx_costs function will try to be helpful by setting the
cost of a multiply to something very high. As this is unlikely
to be appropriate we want to overwrite these costs as soon as
possible.
We start with the assumption that everything will be as expensive
as the cheapest
Hi,
Now the rotates and shifts.
Tested in series on aarch64-none-elf.
OK for stage 1?
Thanks,
James
---
2014-03-27 James Greenhalgh james.greenha...@arm.com
Philipp Tomsich philipp.toms...@theobroma-systems.com
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve
Hi,
When we cost an RTX which touches memory, we really want to cost two
things. The cost of the memory operation, plus some additional cost
if we are using an expensive addressing mode.
This patch adds that modelling.
Tested in series on aarch64-none-elf.
OK for stage 1?
Thanks,
James
---
Hi,
Next up: SIGN_EXTEND, ZERO_EXTEND.
Tested in series on aarch64-none-elf with no regressions.
OK for stage 1?
Thanks,
James
---
2014-03-27 James Greenhalgh james.greenha...@arm.com
Philipp Tomsich philipp.toms...@theobroma-systems.com
* config/aarch64/aarch64.c
Hi,
And now - TRUNCATE.
Tested in series on aarch64-none-elf
OK For stage 1?
Thanks,
James
---
2014-03-27 Philipp Tomsich philipp.toms...@theobroma-systems.com
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost TRUNCATE.
diff --git a/gcc/config/aarch64/aarch64.c
Hi,
MULT, fused/chained multiply with add, and similar operations
with MINUS and NEG should all be handled in a consistent way.
To do that, we can pull out a common mult core from the partial
implementations found around aarch64_rtx_costs.
This patch performs that refactoring. One additional
Hi,
If we are unable to fully cost an RTX, we should return the default
cost and avoid recursing to the operands. This will bias us towards
picking bigger RTX - which presumably have been added as patterns
because somebody expects them to be more efficient.
To aid future debugging and
One of the users within IBM noticed that we did not provide builtins for the
XXSLDWI (vector shift left) and XXPERMDI (permute 64-bit values to make 128-bit
vector) instructions. It turns out, we had provided these builtins, but we had
not documented them, nor did we add them to altivec.h with a
Hi,
This one adds FMA, FLOAT_EXTEND, FLOAT_TRUNCATE, ABS.
and SMAX/SMIN.
Tested in series on aarch64-none-elf.
OK for stage 1?
Thanks,
James
---
2014-03-27 James Greenhalgh james.greenha...@arm.com
Philipp Tomsich philipp.toms...@theobroma-systems.com
*
Hi,
This patch series improves the costing model in the AArch64 backend to
match a number of new idioms.
This patch is a combination of a series I had been working on, with the
cost-model for XGene-1 proposed by Philipp Tomsich.
( http://gcc.gnu.org/ml/gcc-patches/2014-02/msg01084.html )
Where
On Thu, Mar 27, 2014 at 1:43 PM, Michael Meissner
meiss...@linux.vnet.ibm.com wrote:
One of the users within IBM noticed that we did not provide builtins for the
XXSLDWI (vector shift left) and XXPERMDI (permute 64-bit values to make
128-bit
vector) instructions. It turns out, we had
On 25/03/14 17:25 +, Jonathan Wakely wrote:
Tested x86_64-linux, I plan to commit this to trunk soon.
commit 06a845f80204947afd6866109db58cc85dc87117
Author: Jonathan Wakely jwak...@redhat.com
Date: Tue Mar 25 14:42:45 2014 +
PR libstdc++/60612
*
ok.
On Thu, Mar 27, 2014 at 9:02 AM, Dehao Chen de...@google.com wrote:
On Wed, Mar 26, 2014 at 4:05 PM, Xinliang David Li davi...@google.com wrote:
is cgraph_init_gid_map called after linking?
Oh, forgot that part. It's interesting that the test can pass without
another cgraph_init_gid_map
On Thu, Mar 27, 2014 at 02:06:23PM -0400, David Edelsohn wrote:
Thanks for fixing the missing functions and documentation.
Just to clarify the explanation, the builtin name remains
__builtin_vsx_xxx, but the altivec.h macro definition \ is
vec_xxx.
Okay.
Yes. I can change if desired,
The three attachments have been committed as well as another commit to
regenerate the HTML pages.
* doc/xml/manual/io.xml (std.io.objects): Additional markup.
* doc/xml/faq.xml (faq): Refer to clauses instead of chapters.
* doc/xml/manual/appendix_contributing.xml (contrib.design_notes):
On 27 Mar 17:16, Jakub Jelinek wrote:
Which is why the table created for host by the ompexp pass should be
streamed into the target_lto sections (marked specially somehow, special
attribute or whatever), and then corresponding target table created from
that, rather then created from some
Hello,
when trying to build Ada for powerpc64le-linux, I ran into an ICE
in fixup_args_size_notes.
It turns out that the p8 fusion peephole acts on these two insns
from the epilog sequence:
(insn 1693 1078 1079 91 (set (reg:DI 7 7)
(plus:DI (reg/f:DI 31 31)
(const_int 65536
The following patch fixes
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60650
The reason was in general regs pool fragmentation which resulted in
failure to assign double regs to 3 conflicting reload pseudos. The
fragmentation started in IRA and the chain unfortunate events further in
LRA
Bootstrapped/regtested x86_64-linux, comitted.
Not with Ada apparently, resulting in
=== acats tests ===
FAIL: c34007d
FAIL: c34007g
FAIL: c34007s
FAIL: c37213j
FAIL: c37213k
FAIL: c37213l
FAIL: ce2201g
FAIL: cxa5a03
FAIL: cxa5a04
FAIL:
An early * PING* for this wrong-code issue.
Tobias Burnus wrote:
This patch fixes part of the problems of the PR. The problem is that
one assigns an array descriptor to an assumed-rank array descriptor.
The latter has for BT_CLASS the size of max_dim (reason: we have first
the data array and
* PING*
Tobias Burnus wrote:
Hi all,
this patch fixes a problem with the conversion of scalars to
descriptors. There one assigns the address of the scalar to the
base_address field of the descriptor. The ICE occurred when the RHS
(the scalar) wasn't a pointer.
It does not fully solve the
PR c++/60573
* name-lookup.h (cp_binding_level): New field scope_defines_class_p.
* semantics.c (begin_class_definition): Set scope_defines_class_p.
* pt.c (instantiate_class_template_1): Likewise.
* parser.c (synthesize_implicit_template_parm): Use
Hi Tobias,
this patch fixes a problem with the conversion of scalars to descriptors.
There one assigns the address of the scalar to the base_address field of the
descriptor. The ICE occurred when the RHS (the scalar) wasn't a pointer.
looks good to me. Ok for trunk!
It does not fully solve
On 2014-03-27 20:45, Adam Butcher wrote:
@@ -8905,9 +8905,12 @@ instantiate_class_template_1 (tree type)
return type;
/* Now we're really doing the instantiation. Mark the type as in
- the process of being defined. */
+ the process of being defined... */
TYPE_BEING_DEFINED
On 2014-03-27 20:45, Adam Butcher wrote:
PR c++/60573
* name-lookup.h (cp_binding_level): New field scope_defines_class_p.
* semantics.c (begin_class_definition): Set scope_defines_class_p.
* pt.c (instantiate_class_template_1): Likewise.
* parser.c
Hi,
As a followup, the following patch homogeneise some diagnostics that
relate to uninitialized const or reference members.
Tested x86_64 linux in progress, OK to commit for next stage 1 if that
succeeds ? (or trunk otherwise, I dare to mention it).
2014-03-28 Fabien Chêne fab...@gcc.gnu.org
Hi,
This patch is a small optimization for the RL78 target that uses the
'clrb' instruction where possible when performing a zero-extend instead
of 'mov'ing a literal #0. This saves a byte on each operation.
Regards,
Richard
2014-03-27 Richard Hulme pepe...@yahoo.com
*
On Thu, Mar 27, 2014 at 2:49 PM, Ulrich Weigand uweig...@de.ibm.com wrote:
Hello,
when trying to build Ada for powerpc64le-linux, I ran into an ICE
in fixup_args_size_notes.
It turns out that the p8 fusion peephole acts on these two insns
from the epilog sequence:
(insn 1693 1078 1079 91
Whoops, I forgot to document the new builtin. I just committed this change to
the documentation file. Sorry about that.
I also deleted the comment on the nop instruction, just in case there is a VSX
assembler some day that uses a different comment convention.
2014-03-27 Michael Meissner
This is OK after 4.9 branches (i.e. stage1). I suspect we could add
AX to the first alternative, although I don't know if it will get
used. We could add HL to the second alternative to complete the
replacement of the 'r' constraint.
This patch implements the call to the library for code of the form:
caf[j] = (rhs - expr)
Caveats: It currently only handles scalars and for characters only
len-one ones. While it copies also derived types, it does not handle
allocatable components.
With a suitable communication library,
==+
| 4.9.0 20140327 (experimental) [trunk revision 208879] (x86_64-suse-linux)
GCC error:|
| verify_gimple failed |
| Error detected around /home/eric/install/gcc/lib64/gcc/x86_64-suse-
linux/4.9.0/adainclude/a-coorse.adb:1983:4|
You can
Here are more intrinsics that are missing. I know that gcc currently
generates horrible code for most of them but I think it's more important
to have the API in place, albeit non-optimal. Maybe this entices some
one to add the necessary optimizations.
The code is self-contained and shouldn't
PR 59545 points out that there is a case where the Go frontend reads an
invalid value from a class field. This happens because of an incorrect
static_cast. This patch fixes the problem to only use the static_cast
when it is valid. Bootstrapped and ran Go tests on
x86_64-unknown-linux-gnu.
==+
| 4.9.0 20140327 (experimental) [trunk revision 208879] (x86_64-suse-linux)
GCC error:|
| verify_gimple failed |
| Error detected around /home/eric/install/gcc/lib64/gcc/x86_64-suse-
linux/4.9.0/adainclude/a-coorse.adb
88 matches
Mail list logo
