Re: Allow embedded timestamps by C/C++ macros to be set externally (3)

On 16-04-29 09:17:44, Jakub Jelinek wrote: > > Bernd: I'll see if I can prepare a testcase; first I need to get > > familiar with the testing framework and learn how to set environment > > variables in tests. Any tips on that will be really welcome! > > grep for dg-set-target-env-var in various

Re: Allow embedded timestamps by C/C++ macros to be set externally (3)

Hi, I've worked on applying the changes that have been commented in several messages from this thread. Find the patch and changelog attached. On 16-04-29 09:17:44, Jakub Jelinek wrote: > First of all, using error instead of fatal_error achieves just that too, > except that it allows also

[PATCH, i386]: Fix too broad (mem,reg)->(const,reg) splitters

Hello! This patch fixes a bunch of too broad (mem,reg)->(const,reg) splitters, that block other similar splitters. The solution is to check, if the splitter will transform the insn in the splitter condition, instead of using FAIL in the splitter preparation statements. 2016-05-06 Uros Bizjak

[PATCH, ARM] use vmov.i64 to load 0 into FP reg if neon enabled

For this simple testcase double sub (void) { return 0.0; } Without the attached patch, an ARM compiler with neon support enabled, gives vldr.64 d0, .L2 With the attached patch, an ARM compiler with neon enabled, gives vmov.i64 d0, #0@ float which is faster and smaller, as there is no

[PATCHv2,rs6000] Add built-in support for new Power9 darn (deliver a random number) instruction

This patch adds built-in function support for the Power9 darn instruction. This patch and ChangeLog is identical to one I sent earlier today. I have now completed additional testing and made a few changes to my description. I have bootstrapped and tested this patch against the trunk and

Re: [PATCH,rs6000] Add built-in support for new Power9 darn (deliver a random number) instruction

On May 5, 2016 6:26:01 PM GMT+02:00, Kelvin Nilsen wrote: >+ /* Handle simple no-argument operations. */ >+ d = bdesc_0arg; >+ for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++) >+if (d->code == fcode) >+ return rs6000_expand_zeroop_builtin (d->icode,

[PATCH, i386]: Change true_regnum to REGNO in peephole2 and post-reload splitters

Hello! There is no point to determine regno of register operand using true_regnum in peephole2s and post-reload splitters. REGNO can be used instead. 2016-05-05 Uros Bizjak * config/i386/i386.md (peehole2 patterns): Change true_regnum to REGNO in all peephole2

[PATCH], Add PowerPC ISA 3.0 min/max support

This patch was originally meant for GCC 6.x, but the stage3 submission window closed before I could submit this patch. This patch adds support for the new ISA 3.0 instructions for doing min, max, and comparison. Unlike the existing XSMINDP and XSMAXDP instructions, the new XSMINCDP and XSMAXCDP

Re: [PATCH], Add PowerPC ISA 3.0 vector d-form addressing

On Wed, May 04, 2016 at 11:16:52AM -0500, Segher Boessenkool wrote: > Hi Mike, > > On Tue, May 03, 2016 at 06:39:55PM -0400, Michael Meissner wrote: > > With this patch, I enable -mlra if the user did not specify either -mlra or > > -mno-lra on the command line, and -mcpu=power9 or

[PATCH] Make basic asm implicitly clobber memory

Hi! this patch is inspired by recent discussion about basic asm: Currently a basic asm is an instruction scheduling barrier, but not a memory barrier, and most surprising, basic asm does _not_ implicitly clobber CC on targets where extended asm always implicitly clobbers CC, even if nothing is

Re: [v3] Enable dg-reqire-sharedlib on Solaris

On 05/05/16 16:36 +0200, Rainer Orth wrote: I happened to notice that dg-require-sharedlib hardcodes the targets that shared library, and Solaris is missing. Fixed with the following patch. Bootstrapped on i386-pc-solaris2.12, the affected testcases now PASS. Ok for mainline? Looks good -

[PATCH,rs6000] Add built-in support for new Power9 darn (deliver a random number) instruction

This patch adds built-in function support for the Power9 darn instruction. I have bootstrapped and tested on both powerpc64le-unknown-linux-gnu and powerpc64-unknown-linux-gnu with no regressions. Is this ok for trunk and for backpatching to ???. Thanks, Kelvin gcc/testsuite/ChangeLog:

Re: Enabling -frename-registers?

On May 5, 2016, at 6:00 AM, Wilco Dijkstra wrote: > > Ramana Radhakrishnan wrote: >> >> Can you file a bugzilla entry with a testcase that folks can look at please ? > > I created https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70961. Unfortunately > I don't have a simple

[PATCH PR57206]Add test since the PR is fixed by patch to PR48052

Hi, This patch adds a test for PR57206. The issue itself is long fixed by patch to PR48052. Test on x86_64. It's an obvious change, applied on trunk. Thanks bin gcc/testsuite/ChangeLog 2016-05-04 Bin Cheng PR tree-optimization/57206 *

[PATCH PR70935, Regression 6,7]

Hi All, Here is a simple patch which cures the problem with nonlegal transformation of endless loop. THe fix is simply check that guard edge destination is not loop latch block. Bootstrapping and regression testing did not show any new failures. Is it OK for trunk? ChangeLog: 2016-05-05 Yuri

RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi Matthew, Revised patch attached. Tested with mips-img-linux-gnu and bootstrapped x86_64-unknown-linux-gnu. > > mips_gen_const_int_vector > This should use gen_int_for_mode instead of GEN_INT to avoid the issues that > msa_ldi is > trying to handle. gen_int_mode cannot be used to generate a

[patch] Coalesce in more cases

Hi, gimple_can_coalesce_p is rather picky about the conditions under which SSA names can be coalesced. In particular, when it comes to the type, it's: /* Now check the types. If the types are the same, then we should try to coalesce V1 and V2. */ tree t1 = TREE_TYPE (name1); tree

[v3] Enable dg-reqire-sharedlib on Solaris

I happened to notice that dg-require-sharedlib hardcodes the targets that shared library, and Solaris is missing. Fixed with the following patch. Bootstrapped on i386-pc-solaris2.12, the affected testcases now PASS. Ok for mainline? Rainer 2016-05-04 Rainer Orth

Re: Inline across -ffast-math boundary

Richard Biener writes: >> >> This new testcase does not pass on bare-metal configs (using newlib), >> >> because: >> >> warning: implicit declaration of function 'isnanf' >> >> [-Wimplicit-function-declaration] >> >> warning: incompatible implicit declaration of built-in

Re: [PATCH] Better location info for "incomplete type" error msg (PR c/70756)

On Wed, May 04, 2016 at 11:52:39AM -0400, Jason Merrill wrote: > On Wed, May 4, 2016 at 9:00 AM, Marek Polacek wrote: > > On Tue, May 03, 2016 at 08:05:47PM -0400, Jason Merrill wrote: > >> Looks good. > >> > >> But I don't see a C++ testcase; can the test go into

Fix handling of negative bitpos in expand_debug_expr

expand_debug_expr handled negative bit positions using: else if (bitpos < 0) { HOST_WIDE_INT units = (-bitpos + BITS_PER_UNIT - 1) / BITS_PER_UNIT; op0 = adjust_address_nv (op0, mode1, units); bitpos +=

Missing pointer dereference in tree-affine.c

wide_int_constant_multiple_p used: if (*mult_set && mult != 0) return false; to check whether we had previously seen a nonzero multiple, but "mult" is a pointer to the previous value rather than the previous value itself. Noticed by inspection while working on another patch, so I

Re: Improve pure/const propagation across interposable function with non-interposable aliases

Hi Jan, > * gcc.dg/ipa/pure-const-3.c: New testcase. the testcase FAILs: UNRESOLVED: gcc.dg/ipa/pure-const-3.c scan-ipa-dump pure-const "found to be const" The log shows gcc.dg/ipa/pure-const-3.c: dump file does not exist The following patch fixes this. Tested with the appropriate

[committed] Improve gfc_match_omp_clauses

Hi! Before trying to add another 11 new clauses (for OpenMP 4.5), I've realized that we already have way too many to try to match all of them each time; while the matchers are guarded with mask & something, for >= 58 clauses even that is just not too effective and hardly readable as well. So,

Re: [PATCH #3], Fix _Complex when there are multiple FP types the same size

On Mon, May 02, 2016 at 05:10:24PM -0400, Michael Meissner wrote: > [gcc/fortran] > 2016-05-02 Michael Meissner > > * trans-types.c (gfc_build_complex_type): Something missing above... Jakub

Re: [PING][PATCH] New plugin event when evaluating a constexpr call

Hi, thanks for the feedback, I'll do the changes. 2016-05-04 13:16 GMT-03:00 Jason Merrill : > On 05/02/2016 03:28 PM, Andres Tiraboschi wrote: >> >> + constexpr_call_info call_info; >> + call_info.function = t; >> + call_info.call_stack = call_stack; >> + call_info.ctx =

Re: [C++ PATCH] PR c++/69855

On 5 May 2016 at 13:36, Paolo Carlini wrote: > .. minor nit: the new testcase has a number of trailing blank lines. New patch attached. :) 69855.diff5 Description: Binary data

Re: Enabling -frename-registers?

Ramana Radhakrishnan wrote: > > Can you file a bugzilla entry with a testcase that folks can look at please ? I created https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70961. Unfortunately I don't have a simple testcase that I can share. Wilco

[PATCH, i386, AVX-512] Fix sse-14.c (Intel assembly)

Hello, The attached patch fixes sse-14.c to compile with -masm=intel. Bootstrapped. No regressions detected. Please have a look. Is it ok for trunk? 2016-05-05 Petr Murzin gcc/ * config/i386/sse.md: Use proper operand modifiers. * config/i386/i386.c

Re: [PATCH] Improve _fmadd__mask3

On 05 May 13:33, Jakub Jelinek wrote: > On Thu, May 05, 2016 at 01:01:39PM +0300, Kirill Yukhin wrote: > > Hello Jakub, > > On 04 May 21:31, Jakub Jelinek wrote: > > > Hi! > > > > > > As the testcase can show, we should be using v constraint and generate > > > better code that way. > > > > > >

RE: [PATCH] MIPS: In mips_print_address_operand pass the mode argument to mips_classify_address

Andrew Bennett writes: > gcc/ > * config/mips/mips.c (mips_print_operand_address): Pass the mode > argument to > mips_classify_address. Changelog content should wrap at 74 chars. > I have tested the patch on the mips-mti-elf toolchain and there have > been

[PATCH][ARM] PR target/70830: Avoid POP-{reglist}^ when returning from interrupt handlers

Hi all, In this PR we deal with some fallout from the conversion to unified assembly. We now end up emitting instructions like: pop {r0,r1,r2,r3,pc}^ which is not legal. We have to use an LDM form. There are bugs in two arm.c functions: output_return_instruction and arm_output_multireg_pop.

Re: [PATCH] Improve _fmadd__mask3

On Thu, May 05, 2016 at 01:01:39PM +0300, Kirill Yukhin wrote: > Hello Jakub, > On 04 May 21:31, Jakub Jelinek wrote: > > Hi! > > > > As the testcase can show, we should be using v constraint and generate > > better code that way. > > > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok

Re: [PATCH] Some further XMM16+ improvements

On Thu, May 05, 2016 at 01:34:07PM +0300, Kirill Yukhin wrote: > > So, is the patch ok for trunk with the two testcases turned into > > dg-do assemble tests, or do you want me to repost with that, or add the > > Yv constraint right away, something else? > Nope. Patch is pre-OK. Thanks! Actually,

Re: [C++ PATCH] PR c++/69855

.. minor nit: the new testcase has a number of trailing blank lines. Paolo.

Re: [PATCH] Some further XMM16+ improvements

On 05 May 11:56, Jakub Jelinek wrote: > On Thu, May 05, 2016 at 12:49:57PM +0300, Kirill Yukhin wrote: > > Hi Jakub, > > On 03 May 20:57, Jakub Jelinek wrote: > > > This patch improves code generation e.g. on the first attached testcase > > > and allows accepting the second one. > > > > > > I've

Re: [patch] libstdc++/69703 ignore endianness in codecvt_utf8

On 04/05/16 17:19 +0100, Andre Vieira (lists) wrote: On 20/04/16 18:40, Jonathan Wakely wrote: On 19/04/16 19:07 +0100, Jonathan Wakely wrote: This was reported as a bug in the Filesystem library, but it's actually a problem in the codecvt_utf8 facet that it uses. The fix had a silly typo

Re: [PATCH] Improve _fmadd__mask3

Hello Jakub, On 04 May 21:31, Jakub Jelinek wrote: > Hi! > > As the testcase can show, we should be using v constraint and generate > better code that way. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? > > 2016-05-04 Jakub Jelinek > > *

Re: [PATCH] Some further XMM16+ improvements

On Thu, May 05, 2016 at 12:49:57PM +0300, Kirill Yukhin wrote: > Hi Jakub, > On 03 May 20:57, Jakub Jelinek wrote: > > This patch improves code generation e.g. on the first attached testcase > > and allows accepting the second one. > > > > I've noticed we don't allow TFmode or V1TImode in xmm16+

Re: [PATCH] Some further XMM16+ improvements

Hi Jakub, On 03 May 20:57, Jakub Jelinek wrote: > Hi! > > This patch improves code generation e.g. on the first attached testcase > and allows accepting the second one. > > I've noticed we don't allow TFmode or V1TImode in xmm16+ regs at all, > while they are allowed in xmm0-xmm15, so IMHO

RE: [PATCH] MIPS: Ensure that lo_sums do not contain an unaligned symbol

Hi Andrew, Thanks for working on this it is a painful area. There's a bit more to do but this is cleaning up some sneaky bugs. Can you create a GCC bugzilla entry if you haven't already as we should record where these bugs exist and when they are fixed? See my comments but I think that you are

[PATCH] MIPS: In mips_print_address_operand pass the mode argument to mips_classify_address

Hi, Currently the mips_print_operand_address function ignores its mode argument, and when it calls mips_classify_address it forces the mode argument to be the machine's word mode. This patch makes mips_print_operand_address pass the mode argument provided to it to mips_classify_address, so

Re: [PATCH] Handle also switch for -Wdangling-else

On Wed, May 04, 2016 at 09:54:29PM +0200, Jakub Jelinek wrote: > Hi! > > This patch let us warn about danling else even if there is a switch > without {}s around the body. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? > > 2016-05-04 Jakub Jelinek

Re: [Patch AArch64] Fix PR target/63874

On Thu, Mar 31, 2016 at 2:11 PM, Ramana Radhakrishnan wrote: > Hi, > > In this PR we have a situation where we aren't really detecting > weak references vs weak definitions. If one has a weak definition > that binds locally there's no reason not to put

Re: Enabling -frename-registers?

On Wed, May 4, 2016 at 4:20 PM, Wilco Dijkstra wrote: > Bernd Schmidt wrote: >> On 05/04/2016 03:25 PM, Ramana Radhakrishnan wrote: >>> On ARM / AArch32 I haven't seen any performance data yet - the one place we >>> are concerned >>> about the impact is on Thumb2 code

Re: Fix regrename compare-debug issue

> When scanning addresses inside a debug insn, we shouldn't use normal > base/index classes. This shows as a compare-debug issue on Alpha, where > INDEX_REG_CLASS is NO_REGS, and this prevented a chain from being > renamed with debugging turned on. > > Uros has reported that this patch resolves

Re: [SPARC] Support for --with-{cpu,tune}-{32,64} in sparc*-* targets

> This patch adds support for the --with-{cpu,tune}-{32,64} configure > options to sparc*-* targets. This allows to separately select cpus and > tune options for -m32 and -m64 modes in multilib compilers. SPARC/Linux is not the only SPARC target though. :-) > Tested in sparc64-*-* and

Ping: Re: OpenMP offloading to NVPTX: backend patches

Hi! Now that we are in stage1, I'd like to ping this patch series from Alexander. As those are (mostly) patches against the nvptx backend, they need to be reviewed by NVPTX maintainers, and are needed before the corresponding generic OpenMP offloading and libgomp changes are reviewed. On Wed,

Re: [PATCH][SMS] SMS use loop induction variable analysis instead of depending on doloop optimization

Hi, Bernd Thanks for the review. > > You might want to split it up if there are several logically independent > pieces. I can't quite make sense of it all, and I'm not too familiar with SMS > anyway, so the following is not a complete review, just a selection of issues > I observed. Ok, I

[PATCH 0/7] SMS remove dependence on doloop

Hi, The patch try to remove SMS dependency on doloop pass. With the patch, backend don't have to define doloop_end pattern or activate doloop optimization for SMS pass. According the review comment from Bernd https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01960.html I rewrite some comments and

[PATCH 4/7] SMS remove dependence on doloop: update kernel loop iteration adjustment instruction generation

Hi, SMS transformation would change kernel loop iteration count as new_loop_count = ori_loop_count - stage_count. With doloop optimization, loop_count will hold in count_reg in loop entry. The loop count adjustment instruction could generate as count_reg = count_reg - stage_count before

[PATCH 7/7] SMS remove dependence on doloop: To identify read/write register as loop induction variable

Hi, We use loop induction variable analysis to find count_reg. Without doloop optimization, count_reg might be a READ_WRITE_REG. E.g. while (reg < 0x200) { MEM [++reg:SI] = 5} READ_WRITE_REG won't identify as loop induction variable and SMS will skip the loop. We modify loop-iv.c to identify

[PATCH 6/7] SMS remove dependence on doloop: skip the loop if the loop size too small

Hi, SMS loop versioning will generate extra condition code. If SMS could not find enough overlapping in the loop, it may drop performance. Adding parameter PARAM_SMS_LOOP_MIN_SIZE with default value 8 to skip small loops which may not find enough overlapping instructions. Thanks, Shiva

[PATCH 5/7] SMS remove dependence on doloop: update generate_prolog_epilog for the case without doloop pass

Hi, SMS transformation will generate prolog/epilog which are part of the duplication of the instructions in the loop. Doloop optimization will generate a new register(count_reg) to hold iteration count. Therefore, there will no count_reg reference in the loop (except increment/decrement and

[PATCH 2/7] SMS remove dependence on doloop: Use get_simple_loop_desc to get loop iteration count

Hi, The loop after SMS transformation would at least execute stage_count times (due to the duplication in prolog/epilog). To avoid the loop with loop_count < stage_count execute the sms version loop, SMS will try to get loop iteration count. Currently, SMS would get iteration count by finding

[PATCH 3/7] SMS remove dependence on doloop: Update loop-versioning for the loop with step != 1

Hi, To avoid the loop with loop_count < stage_count execute the SMS version loop, SMS will try to get loop iteration count. If the loop iteration count can't get by compile time, SMS will do loop-versioning which will generate original loop and SMS version loop with runtime checking code. With

[PATCH 1/7] SMS remove dependence on doloop: Use loop induction variable analysis in SMS pass

Hi, SMS transformation would change the kernel loop iteration count. To do this, SMS pass will find the register contain loop count and generate the instructions to adjust loop count. Currently, SMS will try to find count_reg by recognizing doloop_end pattern which means if the target didn't