Re: [PATCH] Fortran -- Handle BOZ in accordance with F2008/2015.

On Fri, Oct 06, 2017 at 09:30:06PM -0700, Jerry DeLisle wrote: > On 10/06/2017 01:34 PM, Steve Kargl wrote: > > All, > > > > I have spent the last few days trying to reconcile the various Fortran > > standards' requirements for handling BOZ. The short story is that J3 > > over the last 27 years

Re: [PATCH] Fortran -- Handle BOZ in accordance with F2008/2015.

On 10/06/2017 01:34 PM, Steve Kargl wrote: > All, > > I have spent the last few days trying to reconcile the various Fortran > standards' requirements for handling BOZ. The short story is that J3 > over the last 27 years has made incompatible changes to the interpretation > of a BOZ (under some

Re: [patch, fortran] Set implicit ASYNCHRONOUS attribute

On 10/04/2017 02:41 PM, Thomas Koenig wrote: > Hello world, > > the attached patch sets the implicit ASYNCHRONPUS according to F2008, > 9.6.2.5: > > # If a variable is used in an asynchronous data transfer statement as > # • an item in an input/output list, > # • a group object in a namelist, or

Re: [patch, fortran] Error for non-contiguous pointers

On 10/03/2017 11:35 AM, Thomas Koenig wrote: > Hello world, > > I have re-thought and simplified the patch for PR49232. > This now uses gfc_is_simply_contiguous, in the > non-strict version.  I have also opted for an error > because, well, the use cases rejected by this are really > errors, and

Re: [RFC] propagate malloc attribute in ipa-pure-const pass

On 6 October 2017 at 06:04, Jan Hubicka wrote: >> Hi Honza, >> Thanks for the detailed suggestions, I have updated the patch accordingly. >> I have following questions on call_summary: >> 1] I added field bool is_return_callee in ipa_call_summary to track >> whether the caller

Re: [PATCH PR79868 ][aarch64] Fix error calls in aarch64 code so they can be translated (version 2)

Ping. Steve Ellcey sell...@cavium.com On Mon, 2017-09-25 at 16:25 -0700, Steve Ellcey wrote: > This is a new version of my patch to fix PR target/79868, where some > error messages are impossible to translate correctly due to how the > strings are dynamically constructed.  It also includes some

Re: [RFA] [PATCH] Add a warning for invalid function casts

On 10/06/17 22:50, Jeff Law wrote: > On 10/06/2017 09:43 AM, Martin Sebor wrote: >> On 10/06/2017 07:25 AM, Bernd Edlinger wrote: >>> On 10/05/17 18:16, Martin Sebor wrote: In my (very quick) tests the warning appears to trigger on all strictly incompatible conversions, even if they are

[PATCH][aarch64] Put vector fnma instruction into canonical form for better code generation.

This patch is a follow up to a discussion at: https://gcc.gnu.org/ml/gcc/2017-06/msg00126.html For some reason the simd version of fnma in aarch64-simd.md is not in the canonical form of having the neg operator on  the first operand and instead has it on the second.  This  results in sub-optimal

Re: [RFA] [PATCH] Add a warning for invalid function casts

On 10/06/2017 09:43 AM, Martin Sebor wrote: > On 10/06/2017 07:25 AM, Bernd Edlinger wrote: >> On 10/05/17 18:16, Martin Sebor wrote: >>> In my (very quick) tests the warning appears to trigger on all >>> strictly incompatible conversions, even if they are otherwise >>> benign, such as: >>> >>>   

Re: [RFA] [PATCH] Add a warning for invalid function casts

On 10/05/2017 03:47 PM, Joseph Myers wrote: > On Thu, 5 Oct 2017, Bernd Edlinger wrote: > >> Maybe it would be good to not warn in type-casts, when they can be >> assumed to be safe, for instance >> void* <-> any pointer (parameter or result), >> uintptr_t <-> any int, any pointer (parameter or

Re: [RFA] [PATCH] Add a warning for invalid function casts

On 10/06/2017 12:06 PM, Bernd Edlinger wrote: On 10/06/17 17:43, Martin Sebor wrote: On 10/06/2017 07:25 AM, Bernd Edlinger wrote: On 10/05/17 18:16, Martin Sebor wrote: In my (very quick) tests the warning appears to trigger on all strictly incompatible conversions, even if they are

[PATCH] Fortran -- Handle BOZ in accordance with F2008/2015.

All, I have spent the last few days trying to reconcile the various Fortran standards' requirements for handling BOZ. The short story is that J3 over the last 27 years has made incompatible changes to the interpretation of a BOZ (under some circumstances). The interpretations in F2008 and F2015

[PATCH] Fix PR80295[aarch64] [7/8 Regression] ICE in __builtin_update_setjmp_buf expander

Thanks a lot for Wilco’s help on this bug. Yes, Aarch64 does NOT do anything wrong. The implementation of __builtin_update_setjmp_buf is not correct. It takes a pointer as an operand and treats the Mode of the pointer as Pmode, which is not correct. a conversion from ptr_mode to Pmode is

Re: tree-complex.c: fix some_nonzerop test over reals (and a bug fix)

Hi Richard, thanks for your quick reply. - Mail original - > De: "Richard Biener" > À: "Laurent Thevenoux" > Cc: "GCC Patches" > Envoyé: Vendredi 6 Octobre 2017 13:42:57 > Objet: Re: tree-complex.c: fix

Re: [PATCH], Add PowerPC ISA 3.0 Atomic Memory Operation functions

On Fri, Oct 06, 2017 at 01:25:33PM -0500, Segher Boessenkool wrote: > Hi! > > On Fri, Oct 06, 2017 at 02:03:43PM -0400, Michael Meissner wrote: > > > Do you really need the mr insns? Can't you express that in the > > > arguments? Perhaps using a union of __int128 with something that > > > is

Re: [PATCH], Add PowerPC ISA 3.0 Atomic Memory Operation functions

Hi! On Fri, Oct 06, 2017 at 02:03:43PM -0400, Michael Meissner wrote: > > Do you really need the mr insns? Can't you express that in the > > arguments? Perhaps using a union of __int128 with something that > > is two long ints? > > My first attempt resulted in the compiler doing move directs

Re: [RFA] [PATCH] Add a warning for invalid function casts

On 10/06/17 17:43, Martin Sebor wrote: > On 10/06/2017 07:25 AM, Bernd Edlinger wrote: >> On 10/05/17 18:16, Martin Sebor wrote: >>> In my (very quick) tests the warning appears to trigger on all >>> strictly incompatible conversions, even if they are otherwise >>> benign, such as: >>> >>>    int

[patch, wwwdocs, committed]

Hi, I just committed the change below. Gerald's bot had no complaints, so I guess this must be OK :-) 75a76,78 > The main version of libfortran has been changed to 5. > > 87a91,95 > > When an actual argument contains too few errors for a dummy argument, > an error is now

Re: [PATCH], Add PowerPC ISA 3.0 Atomic Memory Operation functions

On Fri, Oct 06, 2017 at 11:45:10AM -0500, Segher Boessenkool wrote: > Hi Mike, > > On Thu, Oct 05, 2017 at 06:14:14PM -0400, Michael Meissner wrote: > > This patch adds support for most of the PowerPC ISA 3.0 Atomic Memory > > Operation > > instructions, listed in section 4.5 of the manual.

Re: [PATCH] libstdc++: istreambuf_iterator proxy (was: keep attached streambuf)

On Fri, 6 Oct 2017 18:01:36 +0200 François Dumont wrote: > ... > >>> The test itself simulate "stop and go" istream usage. > >>> stringstream is convenient for behaviuor illustration, but in "real life" > >>> I can assume socket or tty on this place. > >> At the very

Re: [PATCH] Implement smart multiple switch expansion algorithms.

Hi. I have watched Martin's talk on switch lowering improvements ( https://slideslive.com/38902416/switch-lowering-improvements), the last slide has a question about benchmarks that can be used for tuning the switch statement optimizer. Martin mentioned one common use case - bytecode interpreters

Re: [PATCH] Implement smart multiple switch expansion algorithms.

On Fri, 2017-10-06 at 14:25 +0200, Martin Liška wrote: > Hello. > > As presented at this year's Cauldron, I rewrote current switch > expansion to support > multiple algorithms (jump table and bit-test) that can be used just > for a fraction > of cases. Balanced decision tree is built on top of

Re: [PATCH] Add sanopt support for UBSAN_PTR.

This looks like an impressive improvement! FWIW, I've been meaning to look into similar opportunities mentioned in bug 79265. Hi. Thank you very much for feedback. If you want I can help with the PR? I belatedly realized I didn't answer one of your questions (or got an answer to one of mine

Re: [PATCH][GCC] Simplification of 1U << (31 - x)

Hi Jakub As per the discussions, I have a created a bug report for the possible regression this may cause. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82454 Sudi From: Wilco Dijkstra Sent: Tuesday, September 26, 2017 2:20 PM To: Sudi Das; Jakub Jelinek Cc: Richard Biener; GCC Patches; nd;

Re: [PATCH], Add PowerPC ISA 3.0 Atomic Memory Operation functions

Hi Mike, On Thu, Oct 05, 2017 at 06:14:14PM -0400, Michael Meissner wrote: > This patch adds support for most of the PowerPC ISA 3.0 Atomic Memory > Operation > instructions, listed in section 4.5 of the manual. Currently these functions > are done via extended asm. At some point in the

Re: [PATCH] Add sanopt support for UBSAN_PTR.

On Fri, Oct 06, 2017 at 10:30:11AM -0600, Martin Sebor wrote: > I think that should work too. ptrdiff_t is usually the same size > as size_t. The two exceptions I could find are VMS and the M32C > target where size_t is always 32-bits wide but ptrdiff_t can be > 64-bits. I don't know what that

Re: [PATCH] Add sanopt support for UBSAN_PTR.

On 10/06/2017 04:18 AM, Martin Liška wrote: On 10/05/2017 07:06 PM, Martin Sebor wrote: On 10/04/2017 03:05 AM, Martin Liška wrote: Hello. Following patch adds support for optimizing out unnecessary UBSAN_PTR checks. It handles separately positive and negative offsets, zero offset is ignored.

Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]

On 06/10/17 13:44, Tamar Christina wrote: > Hi All, > > This is a respin of the patch with the feedback processed. > > Regtested on arm-none-eabi, armeb-none-eabi, > aarch64-none-elf and aarch64_be-none-elf with no issues found. > > Ok for trunk? > > gcc/ > 2017-10-06 Tamar Christina

[PATCH] Add selftest for vec::reverse

Martin: I noticed that your switch expansion patch added a vec::reverse () method. Here's a proposed selftest for it, mostly to verify that it handles even vs odd lengths (which it does). Only lightly tested; hope this is useful. Dave gcc/ChangeLog: * vec.c (selftest::test_reverse):

Re: [PATCH][GCC][testsuite][mid-end][ARM][AARCH64] Fix failing vec align tests.

On 6 October 2017 at 09:45, Tamar Christina wrote: > > >> -Original Message- >> From: Rainer Orth [mailto:r...@cebitec.uni-bielefeld.de] >> Sent: 05 October 2017 20:16 >> To: Tamar Christina >> Cc: gcc-patches@gcc.gnu.org; nd; James Greenhalgh; Richard Earnshaw;

Re: [PATCH] libstdc++: istreambuf_iterator proxy (was: keep attached streambuf)

On 03/10/2017 22:39, Petr Ovtchenkov wrote: On Thu, 28 Sep 2017 13:38:06 +0100 Jonathan Wakely wrote: On 28/09/17 15:06 +0300, Petr Ovtchenkov wrote: On Thu, 28 Sep 2017 11:34:25 +0100 Jonathan Wakely wrote: + VERIFY(i ==

[PR c++/82424] Dont convert dependent types

This fixes crash with -Wshadow=compatible-local, where we ended up trying to convert to or from a dependent type. Rather than skip that out right, I see if the types are the same (dependent or not) before also trying convert in the non-dependent case. I suppose I could try matching

Re: [RFA] [PATCH] Add a warning for invalid function casts

On 10/06/2017 07:25 AM, Bernd Edlinger wrote: On 10/05/17 18:16, Martin Sebor wrote: In my (very quick) tests the warning appears to trigger on all strictly incompatible conversions, even if they are otherwise benign, such as: int f (const int*); typedef int F (int*); F* pf1 = f;

Re: Patch ping

On 10/06/2017 10:12 AM, Jakub Jelinek wrote: Hi! I'd like to ping a couple of patches: http://gcc.gnu.org/ml/gcc-patches/2017-09/msg02006.html PR c++/82299 - invalid -Wuseless-cast on direct enum init Agreed, ok, thanks. nathan -- Nathan Sidwell

Re: Patch ping

On 10/06/2017 10:12 AM, Jakub Jelinek wrote: Hi! I'd like to ping a couple of patches: http://gcc.gnu.org/ml/gcc-patches/2017-09/msg01237.html C++2a P0704R1 - fixing const-qualified pointers to members ok, thanks -- Nathan Sidwell

Re: [PATCH, rs6000] Process deferred rescans between mini-passes

Hi Bill, On Wed, Oct 04, 2017 at 04:44:59PM -0500, Bill Schmidt wrote: > The Power8 swap optimization pass contains a mini-pass to replace certain > patterns prior to swap optimization proper. In order for this not to > distort the dataflow information for swap optimization, we should process >

Re: Allow non-wi wi

> On Oct 6, 2017, at 2:35 AM, Richard Sandiford > wrote: > > Richard Biener writes: >> On Tue, Oct 3, 2017 at 8:34 PM, Richard Sandiford >> wrote: >>> This patch uses global rather than member operators

Re: [PATCH][GRAPHITE] Fix PR82449

On Fri, Oct 6, 2017 at 8:33 AM, Richard Biener wrote: > On Fri, 6 Oct 2017, Sebastian Pop wrote: > > > On Fri, Oct 6, 2017 at 6:56 AM, Richard Biener > wrote: > > > > > > > > The following fences off a few more SCEVs through scev_analyzable_p > given > > >

Re: [GCC][PATCH][TESTSUITE][ARM][COMMITTED] Invert check to misalign in vect_hw_misalign (PR 78421)

On Oct 6, 2017, at 5:48 AM, Tamar Christina wrote: > > I'm looking for permission to backport this patch to the gcc-7 branch to fix > the failing tests there as well. Ok.

RE: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration

Jakub, I completely agree with you. I fixed the patch. Currently, TARGET_PREFER256 will work on architectures with 512VL. It will not work otherwise. I will try to find better solution for this. I think I need to look into register classes to configure available registers for 512F and 512VL in

[C++ PATCH] hash-table for extern-c fns.

This patch converts the extern "C" function map to use a hash table, in the same way as I've just changed namespace bindings. There's a small wart, in that the c_linkage_bindings user (in c-common) expects either a single decl or a TREE_LIST. I.e. not an OVERLOAD. But the hasher expects

Patch ping

Hi! I'd like to ping a couple of patches: http://gcc.gnu.org/ml/gcc-patches/2017-09/msg01237.html C++2a P0704R1 - fixing const-qualified pointers to members

Re: [C++ Patch] PR 47791

On 10/06/2017 08:27 AM, Paolo Carlini wrote: Hi, this is a very old issue, with no impact on the functionality, which I already analyzed a bit a while ago: submitter noticed that finish_function & co could be cleaned up a bit wrt the constants passed in the flags parameter. When I had again

Re: [PATCH] Implement smart multiple switch expansion algorithms.

Martin Liska wrote: > There are some numbers for cc1plus: > > $ bloaty ./objdir2/gcc/cc1plus -- ./objdir/gcc/cc1plus > VM SIZE FILE SIZE > +3.8% +1.11Mi TOTAL +1.03Mi +0.5% > insn-attrtab.o: > VM SIZE FILE SIZE > +214% +682Ki

Re: libbacktrace patch committed: Support compressed debug sections

On Fri, Oct 6, 2017 at 3:22 AM, Gerald Pfeifer wrote: > On Thu, 28 Sep 2017, Ian Lance Taylor wrote: >> This patch to libbacktrace adds support for compressed debug sections. >> 2017-09-28 Ian Lance Taylor >> >> PR other/67165 >> * elf.c

Re: [PATCH] Add -fsanitize=pointer-{compare,subtract}.

On Fri, Oct 06, 2017 at 02:46:05PM +0200, Martin Liška wrote: > + if (sanitize_comparison_p) > + { > + if (is_gimple_assign (s) > + && gimple_assign_rhs_class (s) == GIMPLE_BINARY_RHS > + && POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (s))) > +

Re: [PATCH][GRAPHITE] Fix PR82449

On Fri, 6 Oct 2017, Sebastian Pop wrote: > On Fri, Oct 6, 2017 at 6:56 AM, Richard Biener wrote: > > > > > The following fences off a few more SCEVs through scev_analyzable_p given > > at the end we need those pass chrec_apply when getting a rename through > > SCEV. > > > >

Re: [RFA] [PATCH] Add a warning for invalid function casts

On 10/05/17 18:16, Martin Sebor wrote: > In my (very quick) tests the warning appears to trigger on all > strictly incompatible conversions, even if they are otherwise > benign, such as: > >   int f (const int*); >   typedef int F (int*); > >   F* pf1 = f;    //

Re: [PATCH][AArch64] Fix ICE caused in aarch64_simd_valid_immediate

Hi Sudi, Committed as r253490 on your behalf. Thanks, Tamar From: gcc-patches-ow...@gcc.gnu.org on behalf of Sudi Das Sent: Friday, October 6, 2017 2:19:46 PM To: Richard Earnshaw; Jakub Jelinek Cc:

Re: [PATCH] Fix PR82396: qsort comparator non-negative on sorted output

Maxim Kuvyrkov wrote: Note I've committed: https://gcc.gnu.org/ml/gcc-patches/2017-10/msg00309.html which does change qsort to (qsort) like Jakub proposed. > I think that this is the best solution so far.  Could you add a comment like > the following? > == > Ideally, we would call

Re: [PATCH][AArch64] Fix ICE caused in aarch64_simd_valid_immediate

Hi Richard *** gcc/ChangeLog *** 2017-10-05 Sudakshina Das PR target/82440 * config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Only call aarch64_simd_valid_immediate on CONST_VECTORs. (aarch64_reg_or_bic_imm): Likewise. ***

[C++ PATCH] use hash-table for namespace contents

The one remaining case of us pushing things into a namespace using not-their-name is the anonymous namespace. If we can fix that, then we don't need a hash-map, but can just use a hash-table, which is half the size. This patch does both -- it's simpler than doing this change in two steps. We

Re: [RFC] propagate malloc attribute in ipa-pure-const pass

> Hi Honza, > Thanks for the detailed suggestions, I have updated the patch accordingly. > I have following questions on call_summary: > 1] I added field bool is_return_callee in ipa_call_summary to track > whether the caller possibly returns value returned by callee, which > gets rid of

Re: [PATCH][AArch64] Fix ICE caused in aarch64_simd_valid_immediate

On 06/10/17 12:01, Sudi Das wrote: > > Hi Jakub > > I have modified the entries: > > *** gcc/ChangeLog *** > > 2017-10-05 Sudakshina Das > > PR target/82440 > * config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Changed to > to only call

Re: [PATCH][GRAPHITE] Fix PR82449

On Fri, Oct 6, 2017 at 6:56 AM, Richard Biener wrote: > > The following fences off a few more SCEVs through scev_analyzable_p given > at the end we need those pass chrec_apply when getting a rename through > SCEV. > > The SCEV in question is > > {(integer(kind=4)) {0, +, {1,

Re: [PATCH] [graphite] translate reads and writes in a single traversal of memory ops

On Fri, Oct 6, 2017 at 6:27 AM, Richard Biener wrote: > > > Richard, could you please commit this patch, as I will need to figure out > > why my > > ssh keys don't let me to commit the code. I will probably need to update > > the key. > > Done. You probably still

Re: [PATCH v3 1/14] D: The front-end (DMD) language implementation and license.

Thanks, Ian! -- Andrei

Re: [PATCH v3 1/14] D: The front-end (DMD) language implementation and license.

On Fri, Oct 6, 2017 at 1:34 AM, Iain Buclaw wrote: > > Out of curiosity, I did have a look at some of the tops of gofrontend > sources this morning. They are all copyright the Go Authors, and are > licensed as BSD. So I'm not sure if having copyright FSF and >

Re: [GCC][PATCH][TESTSUITE][ARM][COMMITTED] Invert check to misalign in vect_hw_misalign (PR 78421)

Hi All, I'm looking for permission to backport this patch to the gcc-7 branch to fix the failing tests there as well. Thanks, Tamar From: Mike Stump Sent: Tuesday, September 26, 2017 5:51:00 PM To: Christophe Lyon Cc: Tamar

Re: Let the target choose a vectorisation alignment

[+arm maintainers] Christophe Lyon writes: > On 18 September 2017 at 15:57, Richard Sandiford > wrote: >> Richard Biener writes: >>> On Mon, Sep 18, 2017 at 1:58 PM, Richard Sandiford >>>

Re: [PATCH][GCC][ARM][AArch64] Testsuite framework changes and execution tests [Patch (8/8)]

Hi All, this is a minor respin of the patch with the comments addressed. Note this patch is now 7/8 in the series. Regtested on arm-none-eabi, armeb-none-eabi, aarch64-none-elf and aarch64_be-none-elf with no issues found. Ok for trunk? gcc/testsuite 2017-10-06 Tamar Christina

[PATCH] Add -fsanitize=pointer-{compare,subtract}.

Hi. Adding a missing functionality mentioned and explained here: https://github.com/google/sanitizers/wiki/AddressSanitizerClangVsGCC-(5.0-vs-7.1)#feature-8 Currently it only works for heap allocated variables. I'm working on support for stack and global variables. The functionality is not

Re: [PATCH][GCC][AArch64] Dot Product SIMD patterns [Patch (5/8)]

Hi All, This is a respin with the feedback suggested. Regtested on arm-none-eabi, armeb-none-eabi, aarch64-none-elf and aarch64_be-none-elf with no issues found. Ok for trunk? gcc/ 2017-10-06 Tamar Christina * config/aarch64/aarch64-builtins.c

Re: [PATCH][GCC][Testsuite][ARM][AArch64] Enable Dot Product for generic tests for ARM and AArch64 [Patch (7/8)]

Hi All, this is a respin with the changes suggested. Note that this patch is no 8/8 in the series. Regtested on arm-none-eabi, armeb-none-eabi, aarch64-none-elf and aarch64_be-none-elf with no issues found. Ok for trunk? gcc/testsuite 2017-10-06 Tamar Christina

Re: [PATCH][GCC][ARM] Dot Product NEON patterns [Patch (2/8)]

Hi All, this is a minor respin with changes echo'd from feedback from aarch64. I assume still OK for trunk. Regtested on arm-none-eabi, armeb-none-eabi, aarch64-none-elf and aarch64_be-none-elf with no issues found. Ok for trunk? gcc/ 2017-10-06 Tamar Christina

Re: [PATCH][GCC][AArch64] Dot Product commandline options [Patch (4/8)]

Hi All, this is the respin with the rewording as requested. Assuming still OK for trunk. Regtested on arm-none-eabi, armeb-none-eabi, aarch64-none-elf and aarch64_be-none-elf with no issues found. Ok for trunk? gcc/ 2017-10-06 Tamar Christina *

Re: [PATCH][GCC][ARM] Dot Product commandline options [Patch (1/8)]

Hi All, This is a respin of the patch with the feedback processed. Regtested on arm-none-eabi, armeb-none-eabi, aarch64-none-elf and aarch64_be-none-elf with no issues found. Ok for trunk? gcc/ 2017-10-06 Tamar Christina * config/arm/arm.h (TARGET_DOTPROD):

Re: Fix profile update in switch conversion

On 10/06/2017 02:18 PM, Jan Hubicka wrote: > Hi, > this patch fixes missing profile updat that triggers during profiledbootstrap. > > Honza Thanks for the fix ;) I've just send patch for more complex switch lowering. It's maybe present also there. Will check. Martin

[C++ Patch] PR 47791

Hi, this is a very old issue, with no impact on the functionality, which I already analyzed a bit a while ago: submitter noticed that finish_function & co could be cleaned up a bit wrt the constants passed in the flags parameter. When I had again a look today cleaning up the code appeared

[PATCH] Implement smart multiple switch expansion algorithms.

Hello. As presented at this year's Cauldron, I rewrote current switch expansion to support multiple algorithms (jump table and bit-test) that can be used just for a fraction of cases. Balanced decision tree is built on top of that. I decided to do a bigger refactoring and put all there 3

[C PATCH] Fix -Wtautological-compare (PR c/82437; #2)

On Thu, Oct 05, 2017 at 11:05:57PM +0200, Marek Polacek wrote: > On Thu, Oct 05, 2017 at 10:34:26PM +0200, Jakub Jelinek wrote: > > Hi! > > > > In warn_tautological_bitwise_comparison, there is even a comment > > mentioning the fact that the types of the two constants might not be the > > same

Fix profile update in switch conversion

Hi, this patch fixes missing profile updat that triggers during profiledbootstrap. Honza * tree-switch-conversion.c (do_jump_if_equal, emit_cmp_and_jump_insns): Update edge counts. Index: tree-switch-conversion.c

Re: [PATCH v2] Add sanopt support for UBSAN_PTR.

On Fri, Oct 06, 2017 at 01:43:20PM +0200, Martin Liška wrote: > Thanks for feedback, all resolved except this one: > > ../../gcc/sanopt.c:561:3: warning: suggest braces around empty body in an > ‘else’ statement [-Wempty-body] >; /* Don't record base_addr + expr_offset, it's not a guarding >

[PATCH][GRAPHITE] Fix PR82449

The following fences off a few more SCEVs through scev_analyzable_p given at the end we need those pass chrec_apply when getting a rename through SCEV. The SCEV in question is {(integer(kind=4)) {0, +, {1, +, 1}_1}_1, + 1}_2 which fails to chrec_apply in the CHREC_LEFT part because that part

Re: Allow non-wi wi

On Fri, Oct 6, 2017 at 11:35 AM, Richard Sandiford wrote: > Richard Biener writes: >> On Tue, Oct 3, 2017 at 8:34 PM, Richard Sandiford >> wrote: >>> This patch uses global rather than member operators for

Re: [PATCH] PR82396 workaround for AArch64 bootstrap failure

On Fri, Oct 6, 2017 at 1:21 AM, Wilco Dijkstra wrote: > r253236 broke AArch64 bootstrap. This is a temporary workaround that > disables qsort checking in the scheduler to enable continued development > and testing on AArch64. This will be removed once the autopref

Re: [PATCH v2] Add sanopt support for UBSAN_PTR.

On 10/06/2017 12:53 PM, Jakub Jelinek wrote: > On Fri, Oct 06, 2017 at 12:21:00PM +0200, Martin Liška wrote: >> +/* Return true when pointer PTR for a given CUR_OFFSET is already sanitized >> + in a given sanitization context CTX. */ >> + >> +static bool >> +has_dominating_ubsan_ptr_check

Re: tree-complex.c: fix some_nonzerop test over reals (and a bug fix)

On Thu, Oct 5, 2017 at 4:41 PM, Laurent Thevenoux wrote: > Hello, > > This patch improves the some_nonzerop(tree t) function from tree-complex.c > file (the function is only used there). > > This function returns true if a tree as a parameter is not the constant 0 (or

Re: [C++ PATCH] Fix comment

On 10/05/2017 05:25 PM, Jason Merrill wrote: On Wed, Oct 4, 2017 at 11:44 AM, Nathan Sidwell wrote: On 10/04/2017 11:29 AM, Jason Merrill wrote: On Wed, Oct 4, 2017 at 10:12 AM, Nathan Sidwell wrote: Hmm, I think the error is in the behavior, not the

Re: [PATCH] [graphite] translate reads and writes in a single traversal of memory ops

On Thu, Oct 5, 2017 at 4:27 PM, Sebastian Pop wrote: > > > On Mon, Oct 2, 2017 at 4:18 AM, Richard Biener > wrote: >> >> On Mon, Oct 2, 2017 at 6:53 AM, Sebastian Pop >> wrote: >> > The patch moves the code that translates

Re: [PATCH][AArch64] Fix ICE caused in aarch64_simd_valid_immediate

Hi Jakub I have modified the entries: *** gcc/ChangeLog *** 2017-10-05 Sudakshina Das PR target/82440 * config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Changed to to only call aarch64_simd_valid_immediate on CONST_VECTORs.

Re: [PATCH v2] Add sanopt support for UBSAN_PTR.

On Fri, Oct 06, 2017 at 12:21:00PM +0200, Martin Liška wrote: > +/* Return true when pointer PTR for a given CUR_OFFSET is already sanitized > + in a given sanitization context CTX. */ > + > +static bool > +has_dominating_ubsan_ptr_check (sanopt_ctx *ctx, tree ptr, > +

Re: libbacktrace patch committed: Support compressed debug sections

On Thu, 28 Sep 2017, Ian Lance Taylor wrote: > This patch to libbacktrace adds support for compressed debug sections. > 2017-09-28 Ian Lance Taylor > > PR other/67165 > * elf.c (__builtin_prefetch): Define if not __GNUC__. > (unlikely): Define. > (SHF_UNCOMPRESSED,

[PATCH v2] Add sanopt support for UBSAN_PTR.

Hi. Thanks for the feedback, I implemented was written in Jakub's feedback. I also added comments explaining all cases that happen for what was mentioned as cases 1-6. It would be easier to send newer version of patch to see how I resolved the feedback. Patch has been tested. Martin >From

Re: [PATCH] Add sanopt support for UBSAN_PTR.

On 10/05/2017 07:06 PM, Martin Sebor wrote: > On 10/04/2017 03:05 AM, Martin Liška wrote: >> Hello. >> >> Following patch adds support for optimizing out unnecessary UBSAN_PTR checks. >> It handles separately positive and negative offsets, zero offset is ignored. >> Apart from that, we utilize

Re: [PATCH][AArch64] Fix ICE caused in aarch64_simd_valid_immediate

On Fri, Oct 06, 2017 at 09:52:35AM +, Sudi Das wrote: > This patch is a fix for PR 82440. > The predicates aarch64_reg_or_bic_imm and aarch64_reg_or_orr_imm missed out on > checking for a CONST_VECTOR before calling aarch64_simd_valid_immediate > function. > Also I think James forgot to add

Re: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration

On Fri, Oct 06, 2017 at 09:33:21AM +, Shalnov, Sergey wrote: > Hi, > GCC uses full 512-bit register in case of moving SF/DF value between two > registers. > The patch avoid 512-bit register usage if "-mprefer-avx256" option used. > > 2017-10-06 Sergey Shalnov >

[PATCH][AArch64] Fix ICE caused in aarch64_simd_valid_immediate

Hi This patch is a fix for PR 82440. The predicates aarch64_reg_or_bic_imm and aarch64_reg_or_orr_imm missed out on checking for a CONST_VECTOR before calling aarch64_simd_valid_immediate function. Also I think James forgot to add the test cases in the original patch submitted. Testing done

Re: Allow non-wi wi

Richard Biener writes: > On Tue, Oct 3, 2017 at 8:34 PM, Richard Sandiford > wrote: >> This patch uses global rather than member operators for wide-int.h, >> so that the first operand can be a non-wide-int type. > > Not sure why we had

[PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration

Hi, GCC uses full 512-bit register in case of moving SF/DF value between two registers. The patch avoid 512-bit register usage if "-mprefer-avx256" option used. 2017-10-06 Sergey Shalnov gcc/ * config/i386/i386.md(*movsf_internal, *movdf_internal):

Re: [PATCH v3 1/14] D: The front-end (DMD) language implementation and license.

On 10/6/2017 1:34 AM, Iain Buclaw wrote: On 6 October 2017 at 02:57, Walter Bright wrote: On 10/5/2017 3:59 AM, Iain Buclaw wrote: On 3 October 2017 at 23:36, Joseph Myers wrote: On Tue, 3 Oct 2017, Jeff Law wrote: /* Copyright (c)

Re: [PATCH] Add sanopt support for UBSAN_PTR.

On Thu, Oct 05, 2017 at 03:52:45PM +0200, Martin Liška wrote: > > Do you really need to handle offset != NULL_TREE? > > If the bit offset is representable in shwi, then it will just be > > in bitpos and offset will be NULL. > > For this: > UBSAN_PTR ([(void *) + 9223372036854775807B], 1); > > I

Re: [PATCH] Fix PR82396: qsort comparator non-negative on sorted output

> On Oct 5, 2017, at 11:28 PM, Alexander Monakov wrote: > > On Thu, 5 Oct 2017, Maxim Kuvyrkov wrote: >> I'm still working on analysis, but it appears to me that Alexander's patch >> (current state of trunk) fails qsort check due to not being symmetric for >> load/store

Re: [PATCH v3 1/14] D: The front-end (DMD) language implementation and license.

On 6 October 2017 at 02:57, Walter Bright wrote: > > > On 10/5/2017 3:59 AM, Iain Buclaw wrote: >> >> On 3 October 2017 at 23:36, Joseph Myers wrote: >>> >>> On Tue, 3 Oct 2017, Jeff Law wrote: >>> /* Copyright (c) 2010-2014 by Digital Mars

[PATCH] Fix PR82397

I am testing the following patch to fix the qsort intransitiveness of dr_group_sort_cmp. The patch removes the overly powerful operand_equal_p checks (handling commutativity ) because those do not mix well with the sorting constraints. I am also testing a followup to address the missed

[PATCH] Testcase for PR82422

Committed. Richard. 2017-10-06 Richard Biener PR tree-optimization/82422 * gcc.dg/graphite/pr82422.c: New testcase. Index: gcc/testsuite/gcc.dg/graphite/pr82422.c === ---

[PATCH] Testcase for PR82421

Which was fixed by the code-gen rewrite. Richard. 2017-10-06 Richard Biener PR tree-optimization/82421 * gcc.dg/graphite/pr82421.c: New testcase. Index: gcc/testsuite/gcc.dg/graphite/pr82421.c

Re: [PATCH] Improve -fstore-merging for bool/enum constants (PR tree-optimization/82434)

On Thu, 5 Oct 2017, Jakub Jelinek wrote: > Hi! > > The following testcase fails, because can_native_encode_type_p doesn't > handle BOOLEAN_TYPE nor ENUMERAL_TYPE (while native_encode_expr handles > those just fine). > But, it isn't just those, can_native_encode_type_p doesn't really make > sense

Re: [PATCH] Fix PR82396: qsort comparator non-negative on sorted output

On 5 October 2017 at 22:28, Alexander Monakov wrote: > On Thu, 5 Oct 2017, Maxim Kuvyrkov wrote: >> I'm still working on analysis, but it appears to me that Alexander's patch >> (current state of trunk) fails qsort check due to not being symmetric for >> load/store analysis

RE: [PATCH][GCC][testsuite][mid-end][ARM][AARCH64] Fix failing vec align tests.

> -Original Message- > From: Rainer Orth [mailto:r...@cebitec.uni-bielefeld.de] > Sent: 05 October 2017 20:16 > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd; James Greenhalgh; Richard Earnshaw; > Marcus Shawcroft > Subject: Re: [PATCH][GCC][testsuite][mid-end][ARM][AARCH64] Fix

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