Re: [RFA][PATCH] Stack clash protection 07/08 -- V4 (aarch64 bits)

On 10/13/2017 02:26 PM, Wilco Dijkstra wrote: > Hi, > > To continue the review of the AArch64 frame code I tried a few examples > to figure out what it does now. For initial_adjust <= 63*1024 and > final_adjust < > 1024 there are no probes inserted as expected, ie. the vast majority of >

[PATCH,committed] PR fortran/82620 -- fix detection of syntax error

I've committed the following patch to fix a problem where gfortran ICEs after detection of a syntax error in an allocate statement. The patch was regression tested on x86_64-*-freebsd. === gfortran Summary === # of expected passes46027 # of expected failures

[PATCH], Add rounding built-ins to the _Float and _FloatX built-in functions

The power9 (running PowerPC ISA 3.0) has a round to integer instruction (XSRQPI) that does various flavors of round an IEEE 128-bit floating point to integeral values. This patch adds the support to the machine independent portion of the compiler, and adds the necessary support for ceilf128,

Re: [patch, fortran, RFC] Interchange indices for FORALL and DO CONCURRENT if profitable

Hi Thomas, In general, I like the idea. I have some minor suggestions below. On Sat, Oct 28, 2017 at 12:03:58AM +0200, Thomas Koenig wrote: > +/* Callback function to determine if an expression is the > + corresponding variable. */ > + > +static int static bool > +has_var (gfc_expr **e,

[patch, fortran, RFC] Interchange indices for FORALL and DO CONCURRENT if profitable

Hello world, this is a draft patch which interchanges the indices for FORALL and DO CONCURRENT loops for cases like PR 82471, where code like DO CONCURRENT( K=1:N, J=1:M, I=1:L) C(I,J,K) = A(I,J,K) + B(I,J,K) END DO led to very poor code because of stride issues. Currently, Graphite

Add -std=c17, -std=gnu17

C17, a bug-fix version of the C11 standard with DR resolutions integrated, will soon go to ballot. This patch adds corresponding options -std=c17, -std=gnu17 (new default version, replacing -std=gnu11 as the default), -std=iso9899:2017. As a bug-fix version of the standard, there is no need for

Re: [PATCH] [testsuite/i386] PR 82268 Correct FAIL when configured --with-cpu

On Fri, Oct 27, 2017 at 11:17 PM, Daniel Santos wrote: > When I originally wrote this test I wasn't wasn't aware of the > --with-cpu configure option, so this change explicitly disables avx to > make sure we choose the sse implementation, even when --with-cpu > specifies

[PATCH] [testsuite/i386] PR 82268 Correct FAIL when configured --with-cpu

When I originally wrote this test I wasn't wasn't aware of the --with-cpu configure option, so this change explicitly disables avx to make sure we choose the sse implementation, even when --with-cpu specifies an arch that has avx support. OK for head? gcc/testsuite/ChangeLog:

Re: [committed][PATCH] Convert sprintf warning code to a dominator walk

On 10/27/2017 12:03 PM, David Malcolm wrote: > On Fri, 2017-10-27 at 10:55 -0600, Jeff Law wrote: >> Prereq for eventually embedding range analysis into the sprintf >> warning >> pass. The only thing that changed since the original from a few days >> ago was the addition of FINAL OVERRIDE to the

[committed] Backports to 7.x

Hi! I've backported following 5 patches to 7.x. The PR81715 one, because it could be risky, is enabled only for -fsanitize=kernel-address which it has been reported for and where it causes major issues for the kernel during sanitization. Bootstrapped/regtested on x86_64-linux and i686-linux,

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On 10/27/2017 02:34 PM, Jakub Jelinek wrote: But when singly inheriting a polymorphic base and thus mapped to the same vptr all but the last dtor will not be in charge, right? Correct. So, if using build_clobber_this for this, instead of clobbering what we clobber we'd just clear the single

[PATCH] Assorted store-merging improvements (PR middle-end/22141)

Hi! The following patch attempts to improve store merging, for the time being it still only optimizes constant stores to adjacent memory. The biggest improvement is handling bitfields, it uses the get_bit_range helper to find the bounds of what can be modified when modifying the bitfield and

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On Fri, Oct 27, 2017 at 02:30:39PM -0400, Nathan Sidwell wrote: > On 10/27/2017 02:18 PM, Jakub Jelinek wrote: > > On Fri, Oct 27, 2017 at 02:10:10PM -0400, Jason Merrill wrote: > > > > If the point is to clear the vptr, why are you also clearing the rest > > > of the object? > > > > Can there

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On 10/27/2017 02:18 PM, Jakub Jelinek wrote: On Fri, Oct 27, 2017 at 02:10:10PM -0400, Jason Merrill wrote: If the point is to clear the vptr, why are you also clearing the rest of the object? Can there be multiple vptr pointers in the object or is there just one? Even if there can be

[PATCH, i386]: Fix PR 82692, Ordered comparisons used for unordered built-ins

Hello! As discussed in the PR, different modes of a FP compare RTX are not strong enough to survive through RTL optimization passes. Attached testcase was miscompiled due to combine changing the mode of FP compare through SELECT_CC_MODE. The solution, implemented in the attached patch, is to

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On Fri, Oct 27, 2017 at 02:10:10PM -0400, Jason Merrill wrote: > On Fri, Oct 27, 2017 at 9:52 AM, Jakub Jelinek wrote: > > On Fri, Oct 27, 2017 at 03:48:41PM +0200, Martin Liška wrote: > >> --- a/gcc/cp/decl.c > >> +++ b/gcc/cp/decl.c > >> @@ -14639,8 +14639,12 @@

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On Fri, Oct 27, 2017 at 9:52 AM, Jakub Jelinek wrote: > On Fri, Oct 27, 2017 at 03:48:41PM +0200, Martin Liška wrote: >> --- a/gcc/cp/decl.c >> +++ b/gcc/cp/decl.c >> @@ -14639,8 +14639,12 @@ implicit_default_ctor_p (tree fn) >> /* Clobber the contents of *this to let the back

Re: [committed][PATCH] Convert sprintf warning code to a dominator walk

On Fri, 2017-10-27 at 10:55 -0600, Jeff Law wrote: > Prereq for eventually embedding range analysis into the sprintf > warning > pass. The only thing that changed since the original from a few days > ago was the addition of FINAL OVERRIDE to the before_dom_children > override function. > >

[PATCH] Simplify _Node_insert_return to avoid including

We can use auto return types and if constexpr to do this without including . * include/bits/node_handle.h (_Node_insert_return::get): Avoid use of std::tie and std::get. Tested powerpc64le-linux, committed to trunk. commit 397d3b68eb53ff6b229ac777a05dff4ae842a19b Author:

[PATCH] List headers in Makefile in alphabetical order

I think this header was going to be called math_specfun.h but was renamed at the last minute, without re-ordering it in the Makefile. * include/Makefile.am: Put headers in alphabetical order. * include/Makefile.in: Regenerate. Tested powerpc64le-linux, committed to trunk.

[PATCH] Remove noexcept from filesystem iterators and operations (LWG 3013, 3014)

These issues haven't been resolved yet, but the discussion is correct that these operations allocate memory, so the proposed resolutions are correct. * include/bits/fs_dir.h (directory_iterator): Remove noexcept from constructors and increment member (LWG 3013).

[PATCH] Make filesystem::file_status default constructor non-explicit (LWG 2787)

Also add tests for experimental::file_status. * include/bits/fs_dir.h (file_status): Make default constructor non-explicit (LWG 2787). * testsuite/27_io/filesystem/file_status/1.cc: New test. * testsuite/experimental/filesystem/file_status/1.cc: New test. Tested

Re: [PATCH, rs6000] (v3) Gimple folding for vec_madd()

On Fri, Oct 27, 2017 at 12:51:56PM -0400, David Edelsohn wrote: > On Fri, Oct 27, 2017 at 11:51 AM, Will Schmidt > wrote: > > [PATCH, rs6000] (v2) Gimple folding for vec_madd() > > > > Add support for gimple folding of the vec_madd() (vector multiply-add) > >

[committed][PATCH] Convert sprintf warning code to a dominator walk

Prereq for eventually embedding range analysis into the sprintf warning pass. The only thing that changed since the original from a few days ago was the addition of FINAL OVERRIDE to the before_dom_children override function. Re-bootstrapped and regression tested on x86. Installing on the

Re: [PATCH] Fix nrv-1.c false failure on aarch64.

On 10/26/2017 05:03 PM, Jeff Law wrote: On 10/18/2017 10:59 AM, Egeyar Bagcioglu wrote: Hello, Test case "guality.exp=nrv-1.c" fails on aarch64. Optimizations reorder the instructions and cause the value of a variable to be checked before its first assignment. The following patch is moving the

Re: [PATCH, rs6000] (v3) Gimple folding for vec_madd()

On Fri, Oct 27, 2017 at 11:51 AM, Will Schmidt wrote: > Hi, > V3. :-) > > [PATCH, rs6000] (v2) Gimple folding for vec_madd() > > Add support for gimple folding of the vec_madd() (vector multiply-add) > intrinsics. > Renamed the define_insn of altivec_vmladduhm to

Re: [PATCH][ARM] Remove movdi_vfp_cortexa8

Hi Wilco, On 16/10/17 12:29, Wilco Dijkstra wrote: ping Kyrill Tkachov wrote: On 14/12/16 16:37, Wilco Dijkstra wrote: Merge the movdi_vfp_cortexa8 pattern into movdi_vfp and remove it to avoid unnecessary duplication and repeating bugs like PR78439 due to changes being applied only to

Re: [PATCH, rs6000 V3] Add Power 8 support to vec_revb

Segher: I still have issues with the . > > +(define_mode_attr VSX_XXBR [(V16QI "q") > > + (V8HI "h") > > + (V4SI "w") > > + (V4SF "w") > > + (V2DF "d") > > + (V2DI "d") > > + (V1TI

Re: [PATCH][ARM] Remove DImode expansions for 1-bit shifts

Hi Wilco, Sorry for the delay. On 16/10/17 12:30, Wilco Dijkstra wrote: ping From: Wilco Dijkstra Sent: 17 January 2017 19:23 To: GCC Patches Cc: nd; Kyrill Tkachov; Richard Earnshaw Subject: [PATCH][ARM] Remove DImode expansions for 1-bit shifts A left shift of 1 can always be

Re: [doc] Remove Tru64 UNIX and IRIX references in install.texi

On 10/27/2017 05:48 AM, Rainer Orth wrote: I happened to notice that install.texi still contains references to the Tru64 UNIX and IRIX ports I've removed in GCC 4.8. I believe it's time now to get rid of those completely. Tested with make doc/gccinstall.info and doc/gccinstall.pdf. Ok for

Re: [PATCH] Change default to -fno-math-errno

No existing glibc version defines math_errhandling based on __NO_MATH_ERRNO__. I'd expect such a change to come with a glibc patch, and indeed a GCC execution test of the value of math_errhandling to make sure the compiler's behavior isn't contradicting what's declared by the runtime

Re: Adjust empty class parameter passing ABI (PR c++/60336)

On 10/27/2017 04:38 AM, Jakub Jelinek wrote: > On Fri, Oct 27, 2017 at 12:31:46PM +0200, Richard Biener wrote: >> I fear it doesn't work at all with LTO (you'll always get the old ABI >> if I read the patch correctly). This is because the function >> computing the size looks at flag_abi_version

Re: [doc] Remove Tru64 UNIX and IRIX references in install.texi

On 10/27/2017 05:48 AM, Rainer Orth wrote: > I happened to notice that install.texi still contains references to the > Tru64 UNIX and IRIX ports I've removed in GCC 4.8. I believe it's time > now to get rid of those completely. > > Tested with make doc/gccinstall.info and doc/gccinstall.pdf. Ok

Re: [RFA][PATCH] Provide a class interface into substitute_and_fold.

On 10/26/2017 12:11 PM, Richard Biener wrote: > On October 26, 2017 6:50:15 PM GMT+02:00, Jeff Law wrote: [ Big snip ] >>> Both patches look ok to me though it would be nice to >>> do the actual composition with a comment that the >>> lattices might be moved here (if all

Re: [03/nn] Allow vector CONSTs

Jeff Law writes: > On 10/23/2017 05:18 AM, Richard Sandiford wrote: >> This patch allows (const ...) wrappers to be used for rtx vector >> constants, as an alternative to const_vector. This is useful >> for SVE, where the number of elements isn't known until runtime. > Right.

Re: [01/nn] Add gen_(const_)vec_duplicate helpers

Jeff Law writes: > On 10/23/2017 05:16 AM, Richard Sandiford wrote: >> This patch adds helper functions for generating constant and >> non-constant vector duplicates. These routines help with SVE because >> it is then easier to use: >> >>(const:M (vec_duplicate:M X)) >> >>

Re: [Patch, fortran] PR81758 - [7/8 Regression] [OOP] Broken vtab

On 10/26/2017 12:20 PM, Andre Vehreschild wrote: > Hi Paul, > > Without having tested the patch, it looks reasonable to me. So ok from my > side. > > - Andre > Seconded, thanks. Jerry

[PATCH, rs6000] update vec_perm testcase

Hi, Update the vec-perm testcase to use 'long long' rather than 'long'. This was a missed typo from when i initially committed the test. Credit given to Carl for noticing this one. OK for trunk? Thanks, -Will diff --git

Re: [07/nn] Add unique CONSTs

Jeff Law writes: > On 10/23/2017 05:21 AM, Richard Sandiford wrote: >> This patch adds a way of treating certain kinds of CONST as unique, >> so that pointer equality is equivalent to value equality. For now it >> is restricted to VEC_DUPLICATE and VEC_SERIES, although the code

Re: [PATCH, rs6000] (v3) Gimple folding for vec_madd()

Hi, V3. :-) [PATCH, rs6000] (v2) Gimple folding for vec_madd() Add support for gimple folding of the vec_madd() (vector multiply-add) intrinsics. Renamed the define_insn of altivec_vmladduhm to fmav8hi4, Refreshed the caller of gen_altivec_vmladduhm to call gen_fmav8hi, and updated the

Re: [07/nn] Add unique CONSTs

On 10/23/2017 05:21 AM, Richard Sandiford wrote: > This patch adds a way of treating certain kinds of CONST as unique, > so that pointer equality is equivalent to value equality. For now it > is restricted to VEC_DUPLICATE and VEC_SERIES, although the code to > generate them remains in the else

Re: [PATCH] RISC-V: Correct and improve the "-mabi" documentation

Committed. On Thu, 26 Oct 2017 09:45:07 PDT (-0700), Palmer Dabbelt wrote: > The documentation for the "-mabi" argument on RISC-V was incorrect. We > chose to treat this as a documentation bug rather than a code bug, and > to make the documentation match what GCC currently does. In the >

Re: [09/nn] Add a fixed_size_mode_pod class

On 10/27/2017 02:35 AM, Richard Biener wrote: > On Thu, Oct 26, 2017 at 9:43 PM, Jakub Jelinek wrote: >> On Thu, Oct 26, 2017 at 02:43:55PM +0200, Richard Biener wrote: >>> On Thu, Oct 26, 2017 at 2:18 PM, Richard Sandiford >>> wrote: Richard

Re: [PATCH] Change default optimization level to -Og

On 10/26/2017 01:50 PM, Jakub Jelinek wrote: > On Thu, Oct 26, 2017 at 05:12:40PM +, Wilco Dijkstra wrote: >> GCC's default optimization level is -O0. Unfortunately unlike other >> compilers, >> GCC generates extremely inefficient code with -O0. It is almost unusable for >> low-level

[PATCH] Change default to -fno-math-errno

GCC currently defaults to -fmath-errno. This generates code assuming math functions set errno and the application checks errno. Very few applications test errno and various systems and math libraries no longer set errno since it is optional. GCC generates much faster code for simple math

Re: [RFC] Make 4-stage PGO bootstrap really working

On 2017.10.27 at 15:03 +0200, Martin Liška wrote: > > And BTW would it make sense to add -gtoggle to stage2 in bootstrap-lto? > > Why do you want to have it there? Am I right that we do not do a stage > comparison with LTO bootstrap? The idea was to trigger -g -flto at least during one stage,

Re: [PATCH, Fortran, v1] Clarify error message of co_reduce

On Fri, Oct 27, 2017 at 12:19:02PM +0200, Andre Vehreschild wrote: > Hi all, > > as noted on IRC is one of the error message in check.c co_reduce misleading. > The attached patch fixes this. The intention of the error message is to tell > that the type of the argument bound to parameter A is of

[PATCH] Implement omp async support for nvptx

[ was: Re: [RFC PATCH] Coalesce host to device transfers in libgomp ] On 10/25/2017 01:38 PM, Jakub Jelinek wrote: And we don't really have the async target implemented yet for NVPTX:(, guess that should be the highest priority after this optimization. Hi, how about this approach: 1 - Move

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On Fri, Oct 27, 2017 at 03:48:41PM +0200, Martin Liška wrote: > --- a/gcc/cp/decl.c > +++ b/gcc/cp/decl.c > @@ -14639,8 +14639,12 @@ implicit_default_ctor_p (tree fn) > /* Clobber the contents of *this to let the back end know that the object > storage is dead when we enter the constructor or

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On 10/27/2017 01:26 PM, Jakub Jelinek wrote: On Fri, Oct 27, 2017 at 01:16:08PM +0200, Martin Liška wrote: On 10/27/2017 12:52 PM, Jakub Jelinek wrote: The decl.c change seems to be only incremental change from a not publicly posted patch rather than the full diff against trunk. Sorry for

Re: [hsa] Add missing guard in OMP gridification

On Fri, Oct 27, 2017 at 03:19:05PM +0200, Martin Jambor wrote: > 2017-10-10 Martin Jambor > > * omp-grid.c (grid_attempt_target_gridification): Also insert a > condition whether loop should be executed at all. Ok, thanks. > --- a/gcc/omp-grid.c > +++

[12/nn] [AArch64] Add const_offset field to aarch64_address_info

This patch records the integer value of the address offset in aarch64_address_info, so that it doesn't need to be re-extracted from the rtx. The SVE port will make more use of this. The patch also uses poly_int64 routines to manipulate the offset, rather than just handling CONST_INTs.

[11/nn] [AArch64] Set NUM_POLY_INT_COEFFS to 2

This patch switches the AArch64 port to use 2 poly_int coefficients and updates code as necessary to keep it compiling. One potentially-significant change is to aarch64_hard_regno_caller_save_mode. The old implementation was written in a pretty conservative way: it changed the default behaviour

[10/nn] [AArch64] Minor rtx costs tweak

aarch64_rtx_costs uses the number of registers in a mode as the basis of SET costs. This patch makes it get the number of registers from aarch64_hard_regno_nregs rather than repeating the calcalation inline. Handling SVE modes in aarch64_hard_regno_nregs is then enough to get the correct SET cost

[09/nn] [AArch64] Pass number of units to aarch64_expand_vec_perm(_const)

This patch passes the number of units to aarch64_expand_vec_perm and aarch64_expand_vec_perm_const, which avoids a to_constant () once GET_MODE_NUNITS is variable. 2017-10-27 Richard Sandiford Alan Hayward David

[08/nn] [AArch64] Pass number of units to aarch64_simd_vect_par_cnst_half

This patch passes the number of units to aarch64_simd_vect_par_cnst_half, which avoids a to_constant () once GET_MODE_NUNITS is variable. 2017-10-27 Richard Sandiford Alan Hayward David Sherwood

[07/nn] [AArch64] Pass number of units to aarch64_reverse_mask

This patch passes the number of units to aarch64_reverse_mask, which avoids a to_constant () once GET_MODE_NUNITS is variable. 2017-10-26 Richard Sandiford Alan Hayward David Sherwood gcc/

[06/nn] [AArch64] Add an endian_lane_rtx helper routine

Later patches turn the number of vector units into a poly_int. We deliberately don't support applying GEN_INT to those (except in target code that doesn't disguish between poly_ints and normal constants); gen_int_mode needs to be used instead. This patch therefore replaces instances of:

[05/nn] [AArch64] Rewrite aarch64_simd_valid_immediate

This patch reworks aarch64_simd_valid_immediate so that it's easier to add SVE support. The main changes are: - make simd_immediate_info easier to construct - replace the while (1) { ... break; } blocks with checks that use the full 64-bit value of the constant - treat floating-point modes as

[04/nn] [AArch64] Rename the internal "Upl" constraint

The SVE port uses the public constraints "Upl" and "Upa" to mean "low predicate register" and "any predicate register" respectively. "Upl" was already used as an internal-only constraint by the addition patterns, so this patch renames it to "Uaa" ("two adds needed"). 2017-10-27 Richard

[03/nn] [AArch64] Rework interface to add constant/offset routines

The port had aarch64_add_offset and aarch64_add_constant routines that did similar things. This patch replaces them with an expanded version of aarch64_add_offset that takes separate source and destination registers. The new routine also takes a poly_int64 offset instead of a HOST_WIDE_INT

[02/nn] [AArch64] Move code around

This patch simply moves code around, in order to make the later patches easier to read, and to avoid forward declarations. It doesn't add the missing function comments because the interfaces will change in a later patch. 2017-10-26 Richard Sandiford

[01/nn] [AArch64] Generate permute patterns using rtx builders

This patch replaces switch statements that call specific generator functions with code that constructs the rtl pattern directly. This seemed to scale better to SVE and also seems less error-prone. As a side-effect, the patch fixes the REV handling for diff==1, vmode==E_V4HFmode and adds missing

[00/nn] AArch64 patches preparing for SVE

This series of patches are the AArch64 changes needed before SVE support goes in. It's based on top of: https://gcc.gnu.org/ml/gcc-patches/2017-09/msg01163.html and Jeff's latest stach-clash protection changes. Series tested on aarch64-linux-gnu. Richard

[hsa] Add missing guard in OMP gridification

Hi, rather embarrasingly, I found out that there is a missing condition to make sure that HSA grid size is zero when the OpenMP loop bounds should preclude the loop from executing at all. I do not know whether I lost is somewhere when preparing patches for trunk or whether I forgot about it from

[PATCH] Append PWD to path when using -fprofile-generate=/some/path.

Hello. It's improvement that I consider still useful even though we're not going to use it for profiled bootstrap. Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. Ready for trunk? Thanks, Martin >From 1a32e0b41b291bef3d58126754834f6c41148ace Mon Sep 17 00:00:00 2001

[PATCH][OBVIOUS] Fix profiledbootstrap.

Hello. So eventually it looks needed fix is much simpler, one just need to rename a folder. Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. I'm going to install it. Martin >From 028b5cc3865bdc77c185172de84627e140030303 Mon Sep 17 00:00:00 2001 From: marxin

Re: [RFC] Make 4-stage PGO bootstrap really working

On 10/25/2017 02:19 PM, Markus Trippelsdorf wrote: On 2017.08.30 at 11:45 +0200, Martin Liška wrote: diff --git a/Makefile.in b/Makefile.in index 78db0982ba2..16b76906ad0 100644 --- a/Makefile.in +++ b/Makefile.in @@ -529,13 +529,14 @@ STAGE1_CONFIGURE_FLAGS = --disable-intermodule

Re: [PATCH] Change default optimization level to -Og

Andrew Pinski wrote: > I think this goes against what most folks are used to.  I know you are > saying most folks are used to a compiler defaulting to optimizations > on but I don't think that is true.  In fact GCC has been this way > since day one. Well it may depend which part of the industry

Re: [PATCH] Provide filesystem::path overloads for file streams (LWG 2676, partial)

On 27/10/17 13:43 +0100, Jonathan Wakely wrote: This implements part of LWG 2676. I haven't added the new members taking wide character strings, because they're only needed on Windows, where the Filesystem library doesn't work yet. I'll send a follow-up patch about those overloads. This patch

Re: [RFC] propagate malloc attribute in ipa-pure-const pass

On Fri, 27 Oct 2017, Jan Hubicka wrote: > > On 25 October 2017 at 20:44, Jan Hubicka wrote: > > >> On 24 October 2017 at 16:26, Jan Hubicka wrote: > > >> >> 2017-10-13 Prathamesh Kulkarni > > >> >> > > >> >> * cgraph.h

[PATCH] Provide filesystem::path overloads for file streams (LWG 2676, partial)

This implements part of LWG 2676. I haven't added the new members taking wide character strings, because they're only needed on Windows, where the Filesystem library doesn't work yet. I'll send a follow-up patch about those overloads. I've implemented these new functions as templates, which

[PATCH] New option saphira for Qualcomm server part

From: Siddhesh Poyarekar This patch adds an mcpu option for the Qualcomm saphira server part. Tested on aarch64 and did not find any regressions resulting from this patch. Siddhesh 2017-10-27 Siddhesh Poyarekar

Re: [RFC] propagate malloc attribute in ipa-pure-const pass

> On 25 October 2017 at 20:44, Jan Hubicka wrote: > >> On 24 October 2017 at 16:26, Jan Hubicka wrote: > >> >> 2017-10-13 Prathamesh Kulkarni > >> >> > >> >> * cgraph.h (set_malloc_flag): Declare. > >> >> * cgraph.c

Re: [RFC, PR 80689] Copy small aggregates element-wise

> On Thu, Oct 26, 2017 at 2:55 PM, Jan Hubicka wrote: > >> I think the limit should be on the number of generated copies and not > >> the overall size of the structure... If the struct were composed of > >> 32 individual chars we wouldn't want to emit 32 loads and 32 stores... >

Re: [RFC] propagate malloc attribute in ipa-pure-const pass

Prathamesh > > OK, thanks! > Thanks, committed as r254140 after following validation: > 1] Bootstrap+test with --enable-languages=all,ada,go on > x86_64-unknown-linux-gnu and ppc64le-linux-gnu. > 2] LTO bootstrap+test on x86_64-unknown-linux-gnu and ppc64le-linux-gnu > 3] Cross tested on arm*-*-*

[PATCH] Define std::filesystem::path::format enum (P0430R2)

This enum doesn't do anything for POSIX systems, so this is a pretty uninteresting change. * include/bits/fs_path.h (path::format): Define new enumeration type. (path(string_type&&), path(const Source&)) (path(InputIterator, InputIterator)) (path(const Source&,

[doc] Update install.texi for Solaris 12 rename

There's one Solaris 12 reference in install.texi that also needs adapting for the Solaris 12 -> 11.4 change. However, instead of simply updating it I chose to update the relevant sections for current binutils versions. Tested with make doc/gccinstall.info doc/gccinstall.pdf and visually

[doc] Remove Tru64 UNIX and IRIX references in install.texi

I happened to notice that install.texi still contains references to the Tru64 UNIX and IRIX ports I've removed in GCC 4.8. I believe it's time now to get rid of those completely. Tested with make doc/gccinstall.info and doc/gccinstall.pdf. Ok for mainline? This falls under my prior

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On Fri, Oct 27, 2017 at 01:16:08PM +0200, Martin Liška wrote: > On 10/27/2017 12:52 PM, Jakub Jelinek wrote: > > The decl.c change seems to be only incremental change from a not publicly > > posted patch rather than the full diff against trunk. > > Sorry for that. Sending full patch. Thanks. >

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On 10/27/2017 12:52 PM, Jakub Jelinek wrote: The decl.c change seems to be only incremental change from a not publicly posted patch rather than the full diff against trunk. Sorry for that. Sending full patch. Martin >From df0cc0c2da18b150b1f0fbef418450a223470d7f Mon Sep 17 00:00:00 2001 From:

[wwwdocs] Document change that ipa-pure-const pass propagates malloc attribute.

Applied the attached patch to changes.html. Thanks, Prathamesh * changes.html: Document change that ipa-pure-const is extended to propagate malloc attribute. Index: changes.html === RCS file:

Re: [PATCH] Zero vptr in dtor for -fsanitize=vptr.

On Fri, Oct 27, 2017 at 12:47:12PM +0200, Martin Liška wrote: > Hello. > > This is small improvement that can catch a virtual call after a lifetime > scope of an object. > > > Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. > > Ready to be installed? The decl.c

Re: [RFC] propagate malloc attribute in ipa-pure-const pass

On 25 October 2017 at 20:44, Jan Hubicka wrote: >> On 24 October 2017 at 16:26, Jan Hubicka wrote: >> >> 2017-10-13 Prathamesh Kulkarni >> >> >> >> * cgraph.h (set_malloc_flag): Declare. >> >> * cgraph.c

[PATCH] Zero vptr in dtor for -fsanitize=vptr.

Hello. This is small improvement that can catch a virtual call after a lifetime scope of an object. Patch can bootstrap on ppc64le-redhat-linux and survives regression tests. Ready to be installed? Martin gcc/cp/ChangeLog: 2017-10-27 Martin Liska * decl.c

Re: Adjust empty class parameter passing ABI (PR c++/60336)

On Fri, 27 Oct 2017, Jakub Jelinek wrote: > On Fri, Oct 27, 2017 at 12:31:46PM +0200, Richard Biener wrote: > > I fear it doesn't work at all with LTO (you'll always get the old ABI > > if I read the patch correctly). This is because the function > > computing the size looks at flag_abi_version

Disable partial reg dependencies for haswell+

Hi, while looking for x86 tuning issues I noticed PR81614 about partial register stalls on core. We currently support two schemes for our of order CPUs - partial register dependencies where registers are renamed always as whole and thus it is important to always write complete register at the

Re: Adjust empty class parameter passing ABI (PR c++/60336)

On Fri, Oct 27, 2017 at 12:31:46PM +0200, Richard Biener wrote: > I fear it doesn't work at all with LTO (you'll always get the old ABI > if I read the patch correctly). This is because the function > computing the size looks at flag_abi_version which isn't saved > per function / TU. > >

Re: Adjust empty class parameter passing ABI (PR c++/60336)

On Fri, 27 Oct 2017, Marek Polacek wrote: > This is my attempt at the empty class ABI change. To recap quickly, the C++ > compiler has used a different calling convention for passing empty classes, > because C++ says they have size 1, while the GCC C extension gives them size > 0. > But this

[PATCH, Fortran, v1] Clarify error message of co_reduce

Hi all, as noted on IRC is one of the error message in check.c co_reduce misleading. The attached patch fixes this. The intention of the error message is to tell that the type of the argument bound to parameter A is of wrong type and not that an unspecific argument has a wrong type. If no one

Re: [09/nn] Add a fixed_size_mode_pod class

On 10/27/2017 09:35 AM, Richard Biener wrote: > On Thu, Oct 26, 2017 at 9:43 PM, Jakub Jelinek wrote: >> On Thu, Oct 26, 2017 at 02:43:55PM +0200, Richard Biener wrote: >>> Can you figure what oldest GCC release supports the C++11/14 POD handling >>> that would be required? >>

Adjust empty class parameter passing ABI (PR c++/60336)

This is my attempt at the empty class ABI change. To recap quickly, the C++ compiler has used a different calling convention for passing empty classes, because C++ says they have size 1, while the GCC C extension gives them size 0. But this difference doesn't mean that they need to be passed

[C++ Patch, obvious] Change invalid_nontype_parm_type_p to return a bool

Hi, today I noticed once more that the function pointlessly still returns an int instead of a bool. Unless somebody complaints, I'm going to apply the below. Tested x86_64-linux. Thanks, Paolo. 2017-10-27 Paolo Carlini * pt.c

Re: [09/nn] Add a fixed_size_mode_pod class

> There's always the possibility of building GCC 4.8 with the other compiler > and then GCC 9+ (?) with GCC 4.8. What an user-friendly solution... > What's the list of other compilers people routinely use? I see various > comments on other compilers in install.texi but those are already saying

Re: [PATCH][AArch64] Simplify frame layout for stack probing

On Thu, Oct 26, 2017 at 04:19:35PM +0100, James Greenhalgh wrote: > On Tue, Jul 25, 2017 at 02:58:04PM +0100, Wilco Dijkstra wrote: > > This patch makes some changes to the frame layout in order to simplify > > stack probing. We want to use the save of LR as a probe in any non-leaf > > function.

Re: [PATCH 06/13] remove sdb and -gcoff from non-target files

On Fri, Oct 27, 2017 at 12:12 AM, Jim Wilson wrote: > On Thu, 2017-10-26 at 11:38 +0200, Richard Biener wrote: >> You can eventually keep the option, marking it as Ignore (like we do >> for options we remove but "keep" for backward compatibility). The >> diagnostic (as

Re: [09/nn] Add a fixed_size_mode_pod class

On Fri, Oct 27, 2017 at 10:35:56AM +0200, Richard Biener wrote: > > I think it is too early for that, we aren't LLVM or Rust that don't really > > care about what build requirements they impose on users. > > That's true, which is why I asked. For me requiring sth newer than GCC 4.8 > would be a

Re: [09/nn] Add a fixed_size_mode_pod class

On Thu, Oct 26, 2017 at 9:43 PM, Jakub Jelinek wrote: > On Thu, Oct 26, 2017 at 02:43:55PM +0200, Richard Biener wrote: >> On Thu, Oct 26, 2017 at 2:18 PM, Richard Sandiford >> wrote: >> > Richard Biener writes: >> >>

Re: [PATCH] Document --coverage and fork-like functions (PR gcov-profile/82457).

On 10/26/2017 06:30 PM, Sandra Loosemore wrote: On 10/26/2017 01:21 AM, Martin Liška wrote: On 10/20/2017 06:03 AM, Sandra Loosemore wrote: On 10/19/2017 12:26 PM, Eric Gallager wrote: On 10/19/17, Martin Liška wrote: Hi. As discussed in the PR, we should be more precise in

Re: [09/nn] Add a fixed_size_mode_pod class

On Thu, Oct 26, 2017 at 9:37 PM, Eric Botcazou wrote: >> Can you figure what oldest GCC release supports the C++11/14 POD handling >> that would be required? > > GCC needs to be buildable by other compilers than itself though. There's always the possibility of building GCC

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