Re: [PATCH, rs6000] Fix AIX test case failures

On Fri, Jul 13, 2018 at 7:15 PM Carl Love wrote: > > On Fri, 2018-07-13 at 16:00 -0500, Segher Boessenkool wrote: > > On Fri, Jul 13, 2018 at 10:51:24AM -0400, David Edelsohn wrote: > > > On AIX it would be calling divtc3, but AIX defaults to 64 bit long > > > double. Either all of these tests

Re: [RFC] Induction variable candidates not sufficiently general

On Fri, Jul 13, 2018 at 6:04 AM, Kelvin Nilsen wrote: > A somewhat old "issue report" pointed me to the code generated for a 4-fold > manually unrolled version of the following loop: > >> while (++len != len_limit) /* this is loop */ >> if

Re: [PATCH] [v2][aarch64] Avoid tag collisions for loads falkor

On 07/13/2018 06:32 PM, Kyrill Tkachov wrote: This looks good to me modulo a couple of minor comments inline. You'll still need an approval from a maintainer. Thanks, I'll send a fixed up version on Monday. +  for (ause= DF_REG_USE_CHAIN (regno); ause; ause = DF_REF_NEXT_REG (ause)) +    {

Re: [PATCH] restore -Warray-bounds for string literals (PR 83776)

On 05/02/2018 01:22 AM, Richard Biener wrote: On Fri, Jan 26, 2018 at 3:16 AM, Martin Sebor wrote: PR tree-optimization/83776 - [6/7/8 Regression] missing -Warray-bounds indexing past the end of a string literal, identified a not-so-recent improvement to constant propagation as the reason for

Re: [PATCH, rs6000] Fix AIX test case failures

On Fri, 2018-07-13 at 16:00 -0500, Segher Boessenkool wrote: > On Fri, Jul 13, 2018 at 10:51:24AM -0400, David Edelsohn wrote: > > On AIX it would be calling divtc3, but AIX defaults to 64 bit long > > double.  Either all of these tests need > > > > /* { dg-require-effective-target longdouble128

Re: [PATCH] restore -Warray-bounds for string literals (PR 83776)

+/* Checks one MEM_REF in REF, located at LOCATION, for out-of-bounds + references to string constants. If VRP can determine that the array + subscript is a constant, check if it is outside valid range. + If the array subscript is a RANGE, warn if it is non-overlapping + with valid

Re: [PATCH, rs6000] Fix AIX test case failures

On Fri, Jul 13, 2018 at 10:51:24AM -0400, David Edelsohn wrote: > On AIX it would be calling divtc3, but AIX defaults to 64 bit long > double. Either all of these tests need > > /* { dg-require-effective-target longdouble128 } */ > > or > > /* { dg-additional-options "-mlong-double-128" {

[PATCH], Remove undocumented -mtoc-fusion from PowerPC

Back in the days when I was developing the extended fusion support for PowerPC (-mpower9-fusion), I added a partially implemented option called toc fusion. The idea was to recognize TOC entries (that normally get split into HIGH/LO_SUM pairs) early on, and keep the pairs together. Unfortunately,

libgo patch committed: Skip zero-sized fields in structs when converting to libffi CIF

The libffi library doesn't understand zero-sized objects. This patch to libgo fixes it so that when we see a zero-sized field in a struct, we just skip it when converting to the libffi data structures. There is no value to pass in any case, so not telling libffi about the field doesn't affect

Re: [PATCH] x86: Tune Skylake, Cannonlake and Icelake as Haswell

On Fri, Jul 13, 2018 at 9:31 AM, Jan Hubicka wrote: >> > We have also noticed that benchmarks on skylake are not good compared to >> > haswell, this nicely explains it. I think this is -march=native regression >> > compared to GCC versions that did not suppored better CPUs than Haswell. >> >

Re: [PATCH] Properly unshare TYPE_SIZE_UNIT/DECL_FIELD_OFFSET (PR86216)

On July 13, 2018 6:52:26 PM GMT+02:00, Eric Botcazou wrote: >> It breaks Ada bootstrap. I guess Ada has variable-size types in >> non-function scope (not sure how TYPE_SIZES_GIMPLIFIED works then >> though). That said, r92495 moved the unshare_expr from layout_type >> to gimplify_one_sizepos.

Go patch commited: Fix parsing of composite literals with omitted pointer types

This patch to the Go frontend fixes parsing of composite literals with omitted pointer types. The frontend could parse omitted pointer typess at the end of the type, but not in the middle, so code like []*[][]int{{{1}}} failed. A test case is in https://golang.org/cl/123477. This fixes

Re: [PATCH, rs6000] Alphabetize prototypes of AltiVec built-in functions in extend.texi

On Tue, Jul 10, 2018 at 06:13:50PM -0500, Kelvin Nilsen wrote: > This patch alphabetizes the list of AltiVec built-in function prototypes that > consume about 15 pages of the gcc.pdf file. As part of the alphabetization > effort, certain functions that should not be documented in this section

Re: [PATCH, rs6000] Add missing logical-op interfaces to emmintrin.h

Hi! On Wed, Jul 11, 2018 at 12:26:24PM -0500, Bill Schmidt wrote: > It was recently brought to our attention that the existing emmintrin.h > header, which was believed to be feature-complete for SSE2 support, is > actually missing four logical-op interfaces: > > _mm_and_si128 >

Re: C++ patch ping

On Fri, Jul 13, 2018 at 12:24:02PM -0400, Nathan Sidwell wrote: > On 07/13/2018 09:49 AM, Jakub Jelinek wrote: > > Hi! > > > > I'd like to ping the following C++ patches: > > > > - PR c++/85515 > >make range for temporaries unspellable during parsing and only > >turn them into spellable

Re: [PATCH] Properly unshare TYPE_SIZE_UNIT/DECL_FIELD_OFFSET (PR86216)

> It breaks Ada bootstrap. I guess Ada has variable-size types in > non-function scope (not sure how TYPE_SIZES_GIMPLIFIED works then > though). That said, r92495 moved the unshare_expr from layout_type > to gimplify_one_sizepos. See gimplify.c:763 and below. -- Eric Botcazou

Re: [PATCH][GCC][AArch64] Updated stack-clash implementation supporting 64k probes. [patch (1/6)]

On 07/12/2018 11:39 AM, Tamar Christina wrote: >>> + >>> + /* Round size to the nearest multiple of guard_size, and calculate the >>> + residual as the difference between the original size and the rounded >>> + size. */ >>> + HOST_WIDE_INT rounded_size = size & -guard_size; >>> +

Re: C++ patch ping

On 07/13/2018 09:49 AM, Jakub Jelinek wrote: - PR c++/3698, PR c++/86208 extern_decl_map & TREE_USED fix (plus 2 untested variants) http://gcc.gnu.org/ml/gcc-patches/2018-07/msg00084.html ok, thanks -- Nathan Sidwell

RE: [PATCH][GCC][AArch64] Updated stack-clash implementation supporting 64k probes. [patch (1/6)]

Hi All, I'm sending an updated patch which makes sure unwind tables are disabled always for tests that do sequence checks so they pass in all configurations. There's no change to the cover letter or implementation. Regards, Tamar > -Original Message- > From: Tamar Christina > Sent:

Re: [PATCH] Fix part of PR86389

On 07/03/2018 07:55 AM, Richard Biener wrote: Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. Richard. From 52aad98947e5cfcb5624ff24f0c557d0029c34fe Mon Sep 17 00:00:00 2001 From: Richard Guenther Date: Tue, 3 Jul 2018 14:04:01 +0200 Subject: [PATCH] fix-pr86389 2018-07-03

RE: [PATCH][GCC][AArch64] Ensure that outgoing argument size is at least 8 bytes when alloca and stack-clash. [Patch (3/6)]

Hi All, I'm sending an updated patch which updates a testcase that hits one of our corner cases. This is an assembler scan only update in a testcase. Regards, Tamar > -Original Message- > From: Tamar Christina > Sent: Wednesday, July 11, 2018 12:21 > To: gcc-patches@gcc.gnu.org > Cc:

RE: [PATCH][GCC][AArch64] Validate and set default parameters for stack-clash. [Patch (3/3)]

Hi All, I am sending an updated patch which takes into account a case where the set parameter value would not be safe to call. No change in the cover letter. Regards, Tamar > -Original Message- > From: Tamar Christina > Sent: Wednesday, July 11, 2018 12:25 > To:

Re: [PATCH] x86: Tune Skylake, Cannonlake and Icelake as Haswell

> > We have also noticed that benchmarks on skylake are not good compared to > > haswell, this nicely explains it. I think this is -march=native regression > > compared to GCC versions that did not suppored better CPUs than Haswell. > > So it > > would be nice to backport it. > > Yes, we

Re: C++ patch ping

On 07/13/2018 09:49 AM, Jakub Jelinek wrote: Hi! I'd like to ping the following C++ patches: - PR c++/85515 make range for temporaries unspellable during parsing and only turn them into spellable for debug info purposes http://gcc.gnu.org/ml/gcc-patches/2018-07/msg00086.html How

[ARM/FDPIC v2 20/21] [ARM][testsuite] FDPIC: Adjust pr43698.c to avoid clash with uclibc.

From: Christophe Lyon uclibc defines bswap_32, so use a different name in this test. 2018-XX-XX Christophe Lyon gcc/testsuite/ * gcc.target/arm/pr43698.c (bswap_32): Rename as my_bswap_32. Change-Id: I2591bd911030814331cabf97ee5cf6cf8124b4f3 diff --git

[ARM/FDPIC v2 21/21] [ARM][testsuite] FDPIC: Skip tests using architecture older than v7

From: Christophe Lyon Since FDPIC requires an architecture >=7, these tests fail because they enforce and older version. They would pass if the compiler didn't bail out though. 2018-07-13 Christophe Lyon * gcc.target/arm/armv6-unaligned-load-ice.c: Add arm_arch

[ARM/FDPIC v2 19/21] [ARM][testsuite] FDPIC: Enable tests on pie_enabled targets

From: Christophe Lyon Some tests have the "nonpic" guard, but pass on arm*-*-uclinuxfdpiceabi because it is in PIE mode by default. Rather than adding this target to all these tests, add the "pie_enabled" effective target. 2018-XX-XX Christophe Lyon gcc/testsuite/ *

[ARM/FDPIC v2 18/21] [ARM][testsuite] FDPIC: Handle *-*-uclinux*

From: Christophe Lyon Add *-*-uclinux* to tests that work on this target. 2018-XX-XX Christophe Lyon gcc/testsuite/ * g++.dg/abi/forced.C: Add *-*-uclinux*. * g++.dg/abi/guard2.C: Likewise. * g++.dg/ext/cleanup-10.C: Likewise. *

[ARM/FDPIC v2 17/21] [ARM][testsuite] FDPIC: Skip tests that don't work in PIC mode

From: Christophe Lyon Some tests fail on arm*-*-uclinuxfdpiceabi because it generates PIC code and they don't support it: skip them. They also fail on arm*-linux* when forcing -fPIC. 2018-XX-XX Christophe Lyon gcc/testsuite/ * gcc.target/arm/eliminate.c: Accept only nonpic

[ARM/FDPIC v2 16/21] [ARM][testsuite] FDPIC: Skip v8-m and v6-m tests that currently produce an ICE

From: Christophe Lyon v6-M and v8-M are not supported currently in FDPIC mode, it's better to skip the tests. 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/testsuite/ * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: Skip on arm*-*-uclinuxfdpiceabi.

[ARM/FDPIC v2 15/21] [ARM][testsuite] FDPIC: Adjust scan-assembler patterns.

From: Christophe Lyon In FDPIC mode, r9 is saved in addition to other registers, so update the expected patterns accordingly. 2018-XX-XX Christophe Lyon Mickaël Guêné * gcc/testsuite/ * gcc.target/arm/interrupt-1.c: Add scan-assembler pattern for

[ARM/FDPIC v2 13/21] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture

From: Christophe Lyon Without this, when we are unwinding across a signal frame we can jump to an even address which leads to an exception. This is needed in __gnu_persnality_sigframe_fdpic() when restoring the PC from the signal frame since the PC saved by the kernel has the LSB bit set to

[ARM/FDPIC v2 14/21] [ARM][testsuite] FDPIC: Skip unsupported tests

From: Christophe Lyon Several tests cannot work on ARM-FDPIC for various reasons: skip them, or skip some directives. gcc.dg/20020312-2.c: Skip since it forces -fno-pic. gcc.target/arm/: * Skip since r9 is clobbered by assembly code: 20051215-1.c mmx-1.c pr61948.c pr77933-1.c

[ARM/FDPIC v2 12/21] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp

From: Christophe Lyon We call __aeabi_read_tp() to get the thread pointer. Since this is a function call, we have to restore the FDPIC register afterwards. 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_load_tp): Add FDPIC support. *

[ARM/FDPIC v2 11/21] [ARM] FDPIC: Add support to unwind FDPIC signal frame

From: Christophe Lyon 2018-XX-XX Christophe Lyon Mickaël Guêné libgcc/ * unwind-arm-common.inc (ARM_SET_R7_RT_SIGRETURN) (THUMB2_SET_R7_RT_SIGRETURN, FDPIC_LDR_R12_WITH_FUNCDESC) (FDPIC_LDR_R9_WITH_GOT, FDPIC_LDR_PC_WITH_RESTORER)

[ARM/FDPIC v2 10/21] [ARM] FDPIC: Implement TLS support.

From: Christophe Lyon Support additional relocations: TLS_GD32_FDPIC, TLS_LDM32_FDPIC, and TLS_IE32_FDPIC. We do not support the GNU2 TLS dialect. 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (tls_reloc): Add TLS_GD32_FDPIC,

[ARM/FDPIC v2 09/21] [ARM] FDPIC: Add support for taking address of nested function

From: Christophe Lyon In FDPIC mode, the trampoline generated to support pointers to nested functions looks like: .wordtrampoline address .wordtrampoline GOT address ldr r12, [pc, #8] ldr r9, [pc, #8] ldr

[ARM/FDPIC v2 08/21] [ARM] FDPIC: Ensure local/global binding for function descriptors

From: Christophe Lyon Use local binding rules to decide whether we can use GOTOFFFUNCDESC to compute the function address. 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_local_funcdesc_p): New function. (legitimize_pic_address): Ensure

[ARM/FDPIC v2 07/21] [ARM] FDPIC: Avoid saving/restoring r9 on stack since it is RO

From: Christophe Lyon 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_compute_save_reg0_reg12_mask): Handle FDPIC. (thumb1_compute_save_core_reg_mask): Likewise. Change-Id: Ib534cf91704cdc740867b46a8fe45fda27894562 diff --git

[ARM/FDPIC v2 06/21] [ARM] FDPIC: Add support for c++ exceptions

From: Christophe Lyon The main difference with existing support is that function addresses are function descriptor addresses instead. This means that all code dealing with function pointers now has to cope with function descriptors instead. For the same reason, Linux kernel helpers can no

[ARM/FDPIC v2 05/21] [ARM] FDPIC: Fix __do_global_dtors_aux and frame_dummy generation

From: Christophe Lyon In FDPIC, we need to make sure __do_global_dtors_aux and frame_dummy are referenced by their address, not by pointers to the function descriptors. 2018-XX-XX Christophe Lyon Mickaël Guêné * libgcc/crtstuff.c: Add support for FDPIC. Change-Id:

[ARM/FDPIC v2 04/21] [ARM] FDPIC: Add support for FDPIC for arm architecture

From: Christophe Lyon The FDPIC register is hard-coded to r9, as defined in the ABI. We have to disable tailcall optimizations if we don't know if the target function is in the same module. If not, we have to set r9 to the value associated with the target module. When generating a symbol

[ARM/FDPIC v2 03/21] [ARM] FDPIC: Force FDPIC related options unless -mno-fdpic is provided

From: Christophe Lyon In FDPIC mode, we set -fPIE unless the user provides -fno-PIE, -fpie, -fPIC or -fpic: indeed FDPIC code is PIC, but we want to generate code for executables rather than shared libraries by default. We also make sure to use the --fdpic assembler option, and select the

[ARM/FDPIC v2 02/21] [ARM] FDPIC: Handle arm*-*-uclinuxfdpiceabi in configure scripts

From: Christophe Lyon The new arm-uclinuxfdpiceabi target behaves pretty much like arm-linux-gnueabi. In order the enable the same set of features, we have to update several configure scripts that generally match targets like *-*-linux*: in most places, we add *-uclinux* where there is already

[ARM/FDPIC v2 00/21] FDPIC ABI for ARM

From: Christophe Lyon Hello, This patch series implements the GCC contribution of the FDPIC ABI for ARM targets. This ABI enables to run Linux on ARM MMU-less cores and supports shared libraries to reduce the memory footprint. Without MMU, text and data segments relative distances are

[ARM/FDPIC v2 01/21] [ARM] FDPIC: Add -mfdpic option support

From: Christophe Lyon 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.opt: Add -mfdpic option. Change-Id: Ie5c4ed7434488933de6133186da09cd3ea1291a7 diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index a1286a4..231c1cb 100644 ---

Re: [PATCH] x86: Tune Skylake, Cannonlake and Icelake as Haswell

On Fri, Jul 13, 2018 at 9:07 AM, Jan Hubicka wrote: >> > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c >> > > > index 9e46b7b136f..762ab89fc9e 100644 >> > > > --- a/gcc/config/i386/i386.c >> > > > +++ b/gcc/config/i386/i386.c >> > > > @@ -137,17 +137,22 @@ const struct

[GCC][PATCH][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks

Hi all, This patch adds an optimisation that exploits the AArch64 BFXIL instruction when or-ing the result of two bitwise and operations with non-overlapping bitmasks (e.g. (a & 0x) | (b & 0x)). Example: unsigned long long combine(unsigned long long a, unsigned long long b) {  

Re: [PATCH] x86: Tune Skylake, Cannonlake and Icelake as Haswell

> > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > > > > index 9e46b7b136f..762ab89fc9e 100644 > > > > --- a/gcc/config/i386/i386.c > > > > +++ b/gcc/config/i386/i386.c > > > > @@ -137,17 +137,22 @@ const struct processor_costs *ix86_cost = NULL; > > > > #define m_CORE2

Re: [PATCH] reject conflicting attributes before calling handlers (PR 86453)

On Fri, 13 Jul 2018 at 17:10, Martin Sebor wrote: > > On 07/13/2018 02:53 AM, Christophe Lyon wrote: > > Hi, > > > > On Thu, 12 Jul 2018 at 00:04, Martin Sebor wrote: > >> > >> The attached change set adjusts the attribute exclusion code > >> to detect and reject incompatible attributes before

[PATCH, middle-end]: Fix PR86511, traps are generated for non-trapping compares

As demonstrated in the PR, middle-end changes the trappines of the compare by expanding non-trapping compare to a combination of setcc/cmove branchless code, e.g. UNLT is split to UNORDERED setcc and LT cmove. The above conversion is invalid w.r.t traps, since UNLT doesn't trap on NaNs, while LT

[PR c++/86374] Name lookup failure in enclosing template

This was a latent problem exposed by Jason's fix for 85815. There we needed to find the class in the scope stack. Unfortunately, here we'd pushed an (incomplete) instantiation list, rather than the general template list. We were previously getting away with that because we'd do the lookup

Re: [PATCH] reject conflicting attributes before calling handlers (PR 86453)

On 07/13/2018 02:53 AM, Christophe Lyon wrote: Hi, On Thu, 12 Jul 2018 at 00:04, Martin Sebor wrote: The attached change set adjusts the attribute exclusion code to detect and reject incompatible attributes before attribute handlers are called to have a chance to make changes despite the

Re: [PATCH] S/390: libstdc++: 64 and 32 bit baseline update

On Jul 13 2018, Andreas Krebbel wrote: > @@ -5645,3 +5657,5 @@ OBJECT:8:_ZTTSi@@GLIBCXX_3.4 > OBJECT:8:_ZTTSo@@GLIBCXX_3.4 > OBJECT:8:_ZTTSt13basic_istreamIwSt11char_traitsIwEE@@GLIBCXX_3.4 > OBJECT:8:_ZTTSt13basic_ostreamIwSt11char_traitsIwEE@@GLIBCXX_3.4 >

Re: [PATCH, rs6000] Fix AIX test case failures

On Mon, Jun 25, 2018 at 1:04 PM Segher Boessenkool wrote: > > On Mon, Jun 25, 2018 at 09:53:17AM -0700, Carl Love wrote: > > On Mon, 2018-06-25 at 04:44 -0500, Segher Boessenkool wrote: > > > On Fri, Jun 22, 2018 at 02:55:44PM -0700, Carl Love wrote: > > > > ---

Re: [PATCH][Middle-end][version 3]3rd patch of PR78809

thank you. the patch was just committed into trunk as: https://gcc.gnu.org/viewcvs/gcc?view=revision=262636 Qing > On Jul 12, 2018, at 12:03 PM, Jeff Law wrote: > >> >> gcc/ChangeLog: >> >> +2018-07-11 Qing Zhao >> + >> +PR

C++ patch ping

Hi! I'd like to ping the following C++ patches: - PR c++/85515 make range for temporaries unspellable during parsing and only turn them into spellable for debug info purposes http://gcc.gnu.org/ml/gcc-patches/2018-07/msg00086.html - PR c++/3698, PR c++/86208 extern_decl_map & TREE_USED

Re: C++ PATCH for c++/86190, bogus -Wsign-conversion warning

Ping. On Tue, Jul 03, 2018 at 09:35:24AM -0400, Marek Polacek wrote: > This PR complains about bogus -Wsign-conversion warning even with an > explicit static_cast. It started with this hunk from the delayed folding > merge: > > @@ -5028,20 +5022,12 @@ cp_build_binary_op (location_t location, >

Re: [PATCH] x86: Tune Skylake, Cannonlake and Icelake as Haswell

On Fri, Jul 13, 2018 at 3:12 PM, H.J. Lu wrote: > On Fri, Jul 13, 2018 at 08:53:02AM +0200, Uros Bizjak wrote: > > On Thu, Jul 12, 2018 at 9:57 PM, H.J. Lu wrote: > > > > > r259399, which added PROCESSOR_SKYLAKE, disabled many x86 optimizations > > > which are enabled by PROCESSOR_HASWELL. As

Re: abstract wide int binop code from VRP

On Fri, Jul 13, 2018 at 3:18 PM Richard Biener wrote: > > On Fri, Jul 13, 2018 at 10:05 AM Aldy Hernandez wrote: > > > > > > > > On 07/13/2018 03:02 AM, Richard Biener wrote: > > > On Thu, Jul 12, 2018 at 10:12 AM Aldy Hernandez wrote: > > > > > So besides the general discussion about

Re: abstract wide int binop code from VRP

On Fri, Jul 13, 2018 at 10:05 AM Aldy Hernandez wrote: > > > > On 07/13/2018 03:02 AM, Richard Biener wrote: > > On Thu, Jul 12, 2018 at 10:12 AM Aldy Hernandez wrote: > > > So besides the general discussion about references/pointers for out > > parameters > > let's stay consistet within

Re: [PATCH] x86: Tune Skylake, Cannonlake and Icelake as Haswell

On Fri, Jul 13, 2018 at 08:53:02AM +0200, Uros Bizjak wrote: > On Thu, Jul 12, 2018 at 9:57 PM, H.J. Lu wrote: > > > r259399, which added PROCESSOR_SKYLAKE, disabled many x86 optimizations > > which are enabled by PROCESSOR_HASWELL. As the result, -mtune=skylake > > generates slower codes on

Re: [PATCH] [v2][aarch64] Avoid tag collisions for loads falkor

Hi Siddhesh, On 13/07/18 12:26, Siddhesh Poyarekar wrote: Hi, This is a rewrite of the tag collision avoidance patch that Kugan had written as a machine reorg pass back in February. The falkor hardware prefetching system uses a combination of the source, destination and offset to decide which

Re: [PATCH] Properly unshare TYPE_SIZE_UNIT/DECL_FIELD_OFFSET (PR86216)

On Fri, 13 Jul 2018, Jakub Jelinek wrote: > On Fri, Jul 13, 2018 at 01:49:38PM +0200, Richard Biener wrote: > > The testcase in the PR, while previously ICEing because the C++ FE doesn't > > properly capture VLA size fields, now ICEs because gimplification > > introduces SSA uses that appear in a

[PATCH] S/390: libstdc++: 64 and 32 bit baseline update

Obviously I missed doing a refresh for some time already. Do the updates look reasonable? Andreas libstdc++-v3/ChangeLog: 2018-07-13 Andreas Krebbel * config/abi/post/s390-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/s390x-linux-gnu/32/baseline_symbols.txt:

Re: [PATCH] Properly unshare TYPE_SIZE_UNIT/DECL_FIELD_OFFSET (PR86216)

On Fri, Jul 13, 2018 at 01:49:38PM +0200, Richard Biener wrote: > The testcase in the PR, while previously ICEing because the C++ FE doesn't > properly capture VLA size fields, now ICEs because gimplification > introduces SSA uses that appear in a different function than its > definition. This

arm - Add vendor and CPU id information to arm-cpus.in

This patch moves the vendor and CPU id data from driver-arm.c to the main table of CPU data in arm-cpus.in. It then adds rules to parsecpu.awk to build data tables that can be used by the driver for automatic CPU detection when running natively. This is the last major bit of CPU-specific data

[PATCH] Properly unshare TYPE_SIZE_UNIT/DECL_FIELD_OFFSET (PR86216)

The testcase in the PR, while previously ICEing because the C++ FE doesn't properly capture VLA size fields, now ICEs because gimplification introduces SSA uses that appear in a different function than its definition. This happens because there is tree sharing between the functions. For nested

Re: [PATCH][testsuite/guality] Run guality tests with Og

On Fri, 13 Jul 2018, Tom de Vries wrote: > Hi, > > we advertise Og as the optimization level of choice for the standard > edit-compile-debug cycle, but do not run the guality tests for Og with the > default torture options. > > This patch ensures that we test -Og in the guality tests. > >

[PATCH] Fix PR85974

The following patch fixes address difference folding to consider when one operand doesn't need a conversion. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. Richard. 2018-07-13 Richard Biener PR middle-end/85974 * match.pd (addr1 - addr2): Allow either of the

Re: [PATCH][wwwdocs] Mention Cortex-A76 support in GCC 9 changes.html

On 13/07/18 00:26, Gerald Pfeifer wrote: > On Fri, 29 Jun 2018, Kyrill Tkachov wrote: >> This patch adds support for the Arm Cortex-A76 processor in changes.html >> for GCC 9. It enables the AArch64 section of the page and adds the news >> blob there. It also adds an entry to the

[PATCH] [v2][aarch64] Avoid tag collisions for loads falkor

Hi, This is a rewrite of the tag collision avoidance patch that Kugan had written as a machine reorg pass back in February. The falkor hardware prefetching system uses a combination of the source, destination and offset to decide which prefetcher unit to train with the load. This is great when

Re: [PATCH][debug] Reuse debug exprs generated in remap_ssa_name

On Fri, Jul 13, 2018 at 12:09 PM Tom de Vries wrote: > > On 07/09/2018 02:43 PM, Richard Biener wrote: > > On Sun, Jul 8, 2018 at 11:27 AM Tom de Vries wrote: > >> > >> On Sun, Jul 08, 2018 at 11:22:41AM +0200, Tom de Vries wrote: > >>> On Fri, Jul 06, 2018 at 04:38:50PM +0200, Richard Biener

Re: [PATCH][testsuite, guality] Add -fno-ipa-icf in gcc.dg/guality

On Fri, Jul 13, 2018 at 11:18 AM Tom de Vries wrote: > > Hi, > > Optimization fipa-icf breaks debug info (as is noted in PR63572 - "ICF > breaks user debugging experience"), which make guality tests clztest.c, > ctztest.c and sra-1.c unsupported for option combination "-O2 -flto >

[PATCH][testsuite/guality] Run guality tests with Og

Hi, we advertise Og as the optimization level of choice for the standard edit-compile-debug cycle, but do not run the guality tests for Og with the default torture options. This patch ensures that we test -Og in the guality tests. F.i., for gcc.dg/guality there are 45 fails for Og (while there

Re: [PATCH, Ada] RISC-V: Initial riscv linux Ada port.

> I poked at this a little and noticed a difference between the x86_64 > support and the RISC-V support. The RISC-V C language port has char > as unsigned by default. The x86_64 port has char signed by default. > If I add a -fsigned-char option, then the testcase works as expected > for RISC-V.

Re: [PATCH][debug] Reuse debug exprs generated in remap_ssa_name

On 07/09/2018 02:43 PM, Richard Biener wrote: > On Sun, Jul 8, 2018 at 11:27 AM Tom de Vries wrote: >> >> On Sun, Jul 08, 2018 at 11:22:41AM +0200, Tom de Vries wrote: >>> On Fri, Jul 06, 2018 at 04:38:50PM +0200, Richard Biener wrote: On Fri, Jul 6, 2018 at 12:47 PM Tom de Vries wrote:

Re: [testsuite] Minor tweak to 4 Aarch64 testcases

> I used xfail for these testcases in particular because the intrinsics that > they test should be available for both arm and aarch64. > They are currently not implemented on arm, even though they should be. > The other tests that are skipped instead of xfailed test intrinsics that > should only

[PATCH][testsuite, guality] Add -fno-ipa-icf in gcc.dg/guality

Hi, Optimization fipa-icf breaks debug info (as is noted in PR63572 - "ICF breaks user debugging experience"), which make guality tests clztest.c, ctztest.c and sra-1.c unsupported for option combination "-O2 -flto -fuse-linker-plugin -fno-fat-lto-objects". F.i., in clztest.c foo and bar are

[gen/AArch64] Generate helpers for substituting iterator values into pattern names

Given a pattern like: (define_insn "aarch64_frecpe" ...) the SVE ACLE implementation wants to generate the pattern for a particular (non-constant) mode. This patch automatically generates helpers to do that, specifically: // Return CODE_FOR_nothing on failure. insn_code

[testsuite] Robustify target_tls_runtime check

As witnessed by the kludge added for MSP430 and Visium, the check doesn't really work (that's also visible for arm-eabi). Tested on x86_64-suse-linux, visium-elf and arm-eabi, OK for mainline? 2018-07-13 Eric Botcazou * lib/target-supports.exp (check_effective_target_tls_runtime):

Re: [PATCH] reject conflicting attributes before calling handlers (PR 86453)

Hi, On Thu, 12 Jul 2018 at 00:04, Martin Sebor wrote: > > The attached change set adjusts the attribute exclusion code > to detect and reject incompatible attributes before attribute > handlers are called to have a chance to make changes despite > the exclusions. The handlers are not run when a

Re: [testsuite] Minor tweak to 4 Aarch64 testcases

Hi Eric, On 13/07/18 09:23, Eric Botcazou wrote: These 4 Aarch64 testcases use dg-xfail-if to disable themselves on ARM, while all the other equivalent testcases use dg-skip-if. The latter form is better because it doesn't unnecessarily pollute the testsuite report. Tested on arm-eabi, OK for

[testsuite] Minor tweak to 4 Aarch64 testcases

These 4 Aarch64 testcases use dg-xfail-if to disable themselves on ARM, while all the other equivalent testcases use dg-skip-if. The latter form is better because it doesn't unnecessarily pollute the testsuite report. Tested on arm-eabi, OK for the mainline? 2018-07-13 Eric Botcazou

Re: [PATCH, S390] Increase function alignment to 16 bytes

On 07/12/2018 01:34 PM, Robin Dapp wrote: > Hi, > >> Please skip '+  && !opts->x_optimize_size)'. I'm attaching patch >> that will >> set opts->x_flag_align_functions to 0 for -Os. It's part of another batch >> alignment patches I'm preparing. > > done in the attached version and added some

[SPARC] Minor tweak

Tested on SPARC/Solaris, applied on the mainline. 2018-07-13 Eric Botcazou * config/sparc/sparc-protos.h (sparc_compute_frame_size): Delete. * config/sparc/sparc.c (sparc_compute_frame_size): Make static. -- Eric BotcazouIndex: config/sparc/sparc-protos.h

Re: abstract wide int binop code from VRP

On 07/13/2018 03:02 AM, Richard Biener wrote: On Thu, Jul 12, 2018 at 10:12 AM Aldy Hernandez wrote: So besides the general discussion about references/pointers for out parameters let's stay consistet within related APIs. This means wide_int_binop should have a wide_int wide_int_binop

Re: [Patch, Fortran] PR 85599: warn about short-circuiting of logical expressions for non-pure functions

Just noticed another problematic case: Calls to generic interfaces are not detected as implicitly pure, see enhanced test case in attachment. Will look into this problem on the weekend ... Cheers, Janus 2018-07-12 21:43 GMT+02:00 Janus Weil : > Hi all, > > here is a minor update of the patch,

Re: abstract wide int binop code from VRP

On Thu, Jul 12, 2018 at 10:12 AM Aldy Hernandez wrote: > > On 07/11/2018 01:33 PM, Richard Sandiford wrote: > > Aldy Hernandez writes: > >> On 07/11/2018 08:52 AM, Richard Biener wrote: > >>> On Wed, Jul 11, 2018 at 8:48 AM Aldy Hernandez wrote: > > Hmmm, I think we can do better, and

Re: [PATCH] x86: Tune Skylake, Cannonlake and Icelake as Haswell

On Thu, Jul 12, 2018 at 9:57 PM, H.J. Lu wrote: > r259399, which added PROCESSOR_SKYLAKE, disabled many x86 optimizations > which are enabled by PROCESSOR_HASWELL. As the result, -mtune=skylake > generates slower codes on Skylake than before. The same also applies > to Cannonlake and Icelak

Re: [RFC] Induction variable candidates not sufficiently general

On Fri, Jul 13, 2018 at 12:05 AM Kelvin Nilsen wrote: > > A somewhat old "issue report" pointed me to the code generated for a 4-fold > manually unrolled version of the following loop: > > > while (++len != len_limit) /* this is loop */ > > if