[PATCH] aarch64' Android Support

The following patch aims to add support to android for aarch64 architecture. diff --git a/gcc/config.gcc b/gcc/config.gcc index 09fb9ecd2cd..a8b32e34b47 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1022,8 +1022,9 @@ aarch64*-*-freebsd*) tm_defines="${tm_defines} TARGET_DEFAULT_ASYNC_UNW

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

On Tue, Jun 4, 2019 at 5:56 PM Hongtao Liu wrote: > > On Tue, Jun 4, 2019 at 5:21 PM Jakub Jelinek wrote: > > > > On Tue, Jun 04, 2019 at 05:00:05PM +0800, Hongtao Liu wrote: > > > Thanks for reminding, Here is updated: > > > > You've missed some notes. Ok for trunk with: > > 1) the following pa

Go patch committed: Statically allocate constant interface data

This patch to the Go frontend by Cherry Zhang statically allocates constant interface data. When converting a constant to interface, such as interface{}(42) or interface{}("hello"), if the interface escapes, we currently generate a heap allocation to hold the constant value. This patch changes it

[PATCH 11/12] rs6000: Remove wp and wq

wp becomes wa with isa p9tf, and wq is replaced by wa with isa p9kf. To manage to do that, there is the new mode attribute VSisa. 2019-06-04 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wp"): Delete. (define_register_constraint "wq"):

[PATCH 12/12] rs6000: Update direct-move* testcases

This fixes some testcases that the last fifteen or so patches broke. In all these cases we no longer need to set VSX_REG_ATTR: the default value of "wa" is correct. 2019-06-04 Segher Boessenkool gcc/testsuite/ * gcc.target/powerpc/direct-move-double1.c (VSX_REG_ATTR): Delete.

[PATCH 10/12] rs6000: Add p9kf and p9tf isa values

This adds "p9kf" and "p9tf" isa values, to be used for instruction alternatives where KFmode resp. TFmode is used. 2019-06-04 Segher Boessenkool * config/rs6000/rs6000.md (define_attr "isa"): Add p9kf and p9tf. (define_attr "enabled"): Handle those new isa values. --- gcc/co

[PATCH 08/12] rs6000: -> p

We don't need the mode attribute, if we make work for V4SF and V2DF just like for SF and DF. 2019-06-04 Segher Boessenkool * config/rs6000/rs6000.md (define_mode_attr sd): Add values for V4SF and V2DF. * config/rs6000/vsx.md (define_mode_attr VSs): Delete. (r

[PATCH 05/12] rs6000: Simplify for VSX_TI

When used in VSX_TI, is always just "wa". 2019-06-04 Segher Boessenkool * config/rs6000/vsx.md: Replace all that are used with VSX_TI with just "wa". --- gcc/config/rs6000/vsx.md | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/rs6000/

[PATCH 07/12] rs6000: ww->wa in testsuite

I should have factored this series better. Oh well. Near the end, let's call it loose ends. 2019-06-04 Segher Boessenkool gcc/testsuite/ * gcc.target/powerpc/direct-move-float1.c: Use "wa" instead of "ww" constraint. --- gcc/testsuite/gcc.target/powerpc/direct-move-float1.

[PATCH 09/12] rs6000: More simplification

A whole bunch of mode attributes are used only once. Things are easier to read if we just expand those patterns. It's shorter, too. 2019-06-04 Segher Boessenkool * config/rs6000/vsx.md (define_mode_attr VSr4): Delete. (define_mode_attr VSr5): Delete. (define_mode_att

[PATCH 06/12] rs6000: VSa->wa for some more cases

2019-06-04 Segher Boessenkool * config/rs6000/vsx.md (vsx_): Use wa instead of . (vsx_extract__var): Ditto. --- gcc/config/rs6000/vsx.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 625582

[PATCH 03/12] rs6000: Remove Ftrad, Fvsx, Fs; add s and sd

This removes the , , and mode attributes, and creates new and mode attributes instead. is either "s" or "d", depending on whether the mode is single-precision or double-precision floating point; and is either "s" or nothing. 2019-06-04 Segher Boessenkool * config/rs6000/rs6000.m

[PATCH 02/12] rs6000: Simplify for VSX_W

When used in VSX_W, is always just "wa". 2019-06-04 Segher Boessenkool * config/rs6000/vsx.md: Replace all that are used with VSX_W with just "wa". --- gcc/config/rs6000/vsx.md | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff -

[PATCH 01/12] rs6000: Simplify VS[ra]* for VSX_[BDF]

When used in VSX_B, VSX_D, or VSX_F, both and are always just "wa" now. Similarly and . The former of those is always "wa", so we can remove the mode attribute completely. 2019-06-04 Segher Boessenkool * config/rs6000/vsx.md (define_mode_attr VSr2): Delete. (rest of file)

[PATCH 00/12] rs6000: Another batch of constraint simplification

Tested as before. Committing to trunk. Segher gcc/config/rs6000/constraints.md | 9 - gcc/config/rs6000/rs6000.c | 19 - gcc/config/rs6000/rs6000.h | 3 - gcc/config/rs6000/rs6000.md| 105 ++-- gcc/

[PATCH 04/12] rs6000: ww -> wa

"ww" can always be "wa". 2019-06-04 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "ww"): Delete. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000

[PATCH] Integrate non-TBB serial backend support

* include/bits/c++config: Adjust TBB detection logic to select serial PSTL backend if no TBB present. * testsuite/utils/pstl/test_utils.h: Remove check for __PSTL_USE_PAR_POLICIES --- libstdc++-v3/include/bits/c++config | 8 ++-- libstdc++-v3/testsuite/ut

[wwwdocs] Document existence of openacc-gcc-9-branch

Hi, I've pushed a new branch "openacc-gcc-9-branch" to the Git mirror (i.e. as a Git-only branch), for development of OpenACC and related functionality on top of the GCC 9 branch. It's currently based off the gcc-9_1_0-release tag, and contains a number of patches mainly merged from either the ope

Re: Do not ask alias subset query when access patch can not extend

Honza, On 31 May 2019 11:44:09 CEST, Jan Hubicka wrote: >Bootstrapped/regtested x86_64-linux (all languages > * tree-ssa-alias.c (access_patch_may_continue_p): New function. > (aliasing_component_refs_p): Use it. s/patch/path/g I suspect your fingers play tricks on you on

Re: [PATCH] [MIPS] Inhibit trailing .insn if pool is not followed by code

On Mon, 3 Jun 2019, Faraz Shahbazker wrote: > The __pool and __pend symbols are used to mark the beginning and end of > inline constant pools in MIPS16 code regions. However if the pool occurs > at the boundary of a code region and is not followed by further code, > presence of the __pend symbol

Re: PR C++/63149

On Tue, Jun 04, 2019 at 08:26:58PM +0100, Nina Dinka Ranns wrote: ChangeLog entry is missing. > Index: gcc/cp/pt.c > === > --- gcc/cp/pt.c (revision 271709) > +++ gcc/cp/pt.c (working copy) > @@ -26836,7 +26836,7 @@ > st

Re: PR C++/63149

Hi, On 04/06/19 21:26, Nina Dinka Ranns wrote: Good point, dg-do compile is sufficient to demonstrate the issue. I agree. A couple of additional nits, sorry for mentioning only now. C++63149_2.diff Index: gcc/cp/pt.c === ---

Re: [PATCH] rs6000: Fix PR78263: Don't #define vector, pixel, bool for C++ with strict ANSI

Hi! On Tue, Jun 04, 2019 at 11:09:44AM -0500, Bill Schmidt wrote: > + if any), so we do not need to define them as macros. Also, > + avoid defining them as macros for C++ with strict ANSI, as > + this is not compatible. */ > > -#if !defined(__APPLE_ALTIVEC__) > -/* You are allowed to und

Re: [PATCH] warn on returning alloca and VLA (PR 71924, 90549)

On 6/3/19 5:24 PM, Martin Sebor wrote: On 5/31/19 2:46 PM, Jeff Law wrote: On 5/22/19 3:34 PM, Martin Sebor wrote: -Wreturn-local-addr detects a subset of instances of returning the address of a local object from a function but the warning doesn't try to handle alloca or VLAs, or some non-trivi

Re: PR C++/63149

Good point, dg-do compile is sufficient to demonstrate the issue. Amended, new patch attached. Thanks, Nina On Tue, 4 Jun 2019 at 17:53, Paolo Carlini wrote: > > Hi, > > On 04/06/19 18:36, Nina Dinka Ranns wrote: > > +// Test for PR63149 > > +// { dg-do run { target c++11 } } > > Are you sure you

Review Hashtable extract node API

Hi     Here is a patch to enhance the _Hashtable extract node API and fix a FIXME request.     The enhancement to the extract node Api is that extract(const key_type&) do not call extract(const_iterator) anymore. Doing so we had to loop again through bucket nodes to find the previous node to

Re: PR C++/63149

Hi, On 04/06/19 18:36, Nina Dinka Ranns wrote: +// Test for PR63149 +// { dg-do run { target c++11 } } Are you sure you want a dg-do run? Paolo.

PR C++/63149

Tested on Linux x86_64 2019-06-04 Nina Dinka Ranns gcc/cp PR c++/63149 * pt.c (listify_autos): use non cv qualified auto_node in std::initializer_list testsuite/ PR c++/63149 * g++.dg/cpp0x/initlist-deduce.C: New Index: gcc/cp/pt.c =

[PATCH 7/7] rs6000: wf -> wa

"wf" is just "wa". 2019-06-04 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wf"): Delete. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.h (en

[PATCH 6/7] rs6000: wd -> wa

"wd" is just "wa". 2019-06-04 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wd"): Delete. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.h (en

[PATCH 5/7] rs6000: Delete Fv2

always is "wa". 2019-06-04 Segher Boessenkool * config/rs6000/rs6000.md (define_mode_attr Fv2): Delete. (rest of file): Adjust. --- gcc/config/rs6000/rs6000.md | 77 + 1 file changed, 36 insertions(+), 41 deletions(-) diff --git

[PATCH 4/7] rs6000: Delete VS_64reg

now always is "wa". Make that simplification. 2019-06-04 Segher Boessenkool * config/rs6000/vsx.md (define_mode_attr VS_64reg): Delete. (*vsx_extract___load): Adjust. (vsx_splat__reg): Adjust. --- gcc/config/rs6000/vsx.md | 9 ++--- 1 file changed, 2 insertions

[PATCH 3/7] rs6000: ws -> wa

"ws" is just "wa". 2019-06-04 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "ws"): Delete. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.h (en

[PATCH 2/7] rs6000: wv -> v+p7v

"wv" is "v", but only if VSX is enabled (otherwise it's NO_REGS). So this patch sets "isa" "p7v" to all alternatives that used "wv" before (and that do not already need a later ISA), and changes the constraint. 2019-06-04 Segher Boessenkool * config/rs6000/constraints.md (define_regi

[PATCH 1/7] rs6000: wi->wa, wt->wa

"wi" and "wt" mean just the same as "wa" these days. Change them to the simpler name. 2019-06-04 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wi"): Delete. (define_register_constraint "wt"): Delete. * config/rs6000/rs6000.c (r

[PATCH 0/7] rs6000: More constraint updates

All tested on p7, p8, p9, powerpc64-linux {-m32,-m64} and powerpc64le-linux. Committing to trunk. Segher gcc/config/rs6000/constraints.md | 18 gcc/config/rs6000/rs6000.c | 28 +- gcc/config/rs6000/rs6000.h | 6 -- gcc/config/rs6000/rs6000.md | 205 +++

Re: [PATCH] aarch64: fix asm visibility for extern symbols

On Tue, Jun 04, 2019 at 03:58:07PM +0100, Szabolcs Nagy wrote: > Commit r271869 broke visibility declarations in asm for extern symbols, > because > the new ASM_OUTPUT_EXTERNAL hook failed to call the default hook for elf. OK. In future, you can consider a patch like this to fall under the "obvi

[PATCH] rs6000: Fix PR78263: Don't #define vector, pixel, bool for C++ with strict ANSI

Hi, We've had a long-standing issue (PR78263) with altivec.h wherein the #define of bool causes difficulties with C++ code with strict ANSI requirements (-std=c++11 versus -std=gnu+11, for example). This patch disables the AltiVec keywords from being #define'd under those circumstances. There is

Re: [C++ Patch] Use declarator->id_loc in three additional places

Hi, On 04/06/19 16:50, Jason Merrill wrote: On 6/4/19 10:31 AM, Paolo Carlini wrote: +  permerror (loc, "member functions are implicitly " + "friends of their class"); Wouldn't it be better to use the location of "friend" in this diagnostic? Yes, however doing that fully

[PATCH V6] Remove empty loop with assumed finiteness (PR tree-optimization/89713)

Some changes on documentation. Feng diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 37aab79..4fdc5c8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2019-06-04 Feng Xue + + PR tree-optimization/89713 + * doc/invoke.texi (-ffinite-loop): Document new option. +

Re: [C++ PATCH] structure tag lookup.

On Tue, Jun 04, 2019 at 11:13:14AM -0400, Nathan Sidwell wrote: > - /* Type found, check if it is in the allowed scopes, ignoring cleanup > - and template parameter scopes. */ > - if (val) > + if (b->kind != sk_namespace) > +/* Look in non-namespace scopes. */ > +for (cxx_binding *

[PATCH V5] Remove empty loop with assumed finiteness (PR tree-optimization/89713)

> Why wouldn't it be suitable for -O2? Normally, not suitable for -O2 could > be because it is expensive (in compile time), because it increases the > code size a lot, because it doesn't always actually improve the running > time, etc. I don't see any of that here. There isn't supposed to be a

[C++ PATCH] structure tag lookup.

lookup of a structure tag, via xref tag, is rather confused, and I found myself wandering into that code. We lookup a tag on the binding scopes, then if that fails we try the innermost enclosing namespace. /Then/ we see if we were allowed to look at the scope we found something in. I've reim

Re: [patch] Fix segfault caused by spurious constant overflow

On Mon, Jun 3, 2019 at 12:38 PM Eric Botcazou wrote: > > > Hmm, ISTR we had such mitigations in place (or have) elsewhere keying > > on the most significant bit set instead of power-of-two. But your case > > likely recurses and runs into the extract_multiv limiting to eventually > > stop, even fo

Re: undefined behavior in value_range::equiv_add()?

On Tue, Jun 4, 2019 at 3:40 PM Jeff Law wrote: > > On 6/4/19 5:23 AM, Richard Biener wrote: > > On Tue, Jun 4, 2019 at 12:30 AM Jeff Law wrote: > >> > >> On 6/3/19 7:13 AM, Aldy Hernandez wrote: > >>> On 5/31/19 5:00 AM, Richard Biener wrote: > On Fri, May 31, 2019 at 2:27 AM Jeff Law wrote

[PATCH] aarch64: fix asm visibility for extern symbols

Commit r271869 broke visibility declarations in asm for extern symbols, because the new ASM_OUTPUT_EXTERNAL hook failed to call the default hook for elf. gcc/ChangeLog: 2019-06-04 Szabolcs Nagy * config/aarch64/aarch64-protos.h (aarch64_asm_output_external): Remove const.

Re: [C++ Patch] Use declarator->id_loc in three additional places

On 6/4/19 10:31 AM, Paolo Carlini wrote: + permerror (loc, "member functions are implicitly " +"friends of their class"); Wouldn't it be better to use the location of "friend" in this diagnostic? The rest of the patch is OK. Jason

Re: [C++ PATCH, PING^3] PR60531 - Wrong error about unresolved overloaded function

Applied, thanks for your persistence. On 5/31/19 3:06 PM, Harald van Dijk wrote: another ping On 12/05/2019 17:57, Harald van Dijk wrote: ping again On 26/04/2019 19:58, Harald van Dijk wrote: ping On 13/04/2019 10:01, Harald van Dijk wrote: Hi, For PR60531, GCC wrongly rejects function t

[C++ PATCH] Reduce accumulated garbage in constexpr evaluation.

We want to evaluate the arguments to a call before looking into the cache so that we have constant values, but if we then find the call in the cache we end up with a TREE_LIST that we don't end up using; in highly recursive constexpr evaluation this ends up being a large proportion of the garbage g

[PATCH] IPA ICF: enhance dump output

Hi. The patch is about simplification of dump output. Plus it prints also a file in which the dump message was emitted. Patch can bootstrap on x86_64-linux-gnu and survives regression tests. Ready to be installed? Thanks, Martin gcc/ChangeLog: 2019-06-04 Martin Liska * ipa-icf-gimp

[PATCH][OBVIOUS] Remove dead code in IPA ICF.

Hi. The patch is about a small clean up, I'm going to install that as obvious. Martin gcc/ChangeLog: 2019-06-04 Martin Liska * ipa-icf.c (INCLUDE_LIST): Remove. (sem_item_optimizer::execute): Remove call to init_wpa. * ipa-icf.h (init_wpa): Remove. --- gcc/ipa-icf.c

[C++ Patch] Use declarator->id_loc in three additional places

Hi, tested x86_64-linux, as usual. Thanks, Paolo. /// /cp 2019-06-04 Paolo Carlini * decl.c (grokdeclarator): Use declarator->id_loc in three additional places. /testsuite 2019-06-04 Paolo Carlini * g++.dg/concepts/pr60573.C: Test locations

Re: [PATCH v2] aarch64: emit .variant_pcs for aarch64_vector_pcs symbol references

On 04/06/2019 13:21, Christophe Lyon wrote: > On Mon, 3 Jun 2019 at 13:28, James Greenhalgh > wrote: >> >> On Wed, May 29, 2019 at 11:00:46AM +0100, Richard Sandiford wrote: >>> Szabolcs Nagy writes: v2: - use aarch64_simd_decl_p to check for aarch64_vector_pcs. - emit the .varian

Re: undefined behavior in value_range::equiv_add()?

On 6/4/19 5:23 AM, Richard Biener wrote: > On Tue, Jun 4, 2019 at 12:30 AM Jeff Law wrote: >> >> On 6/3/19 7:13 AM, Aldy Hernandez wrote: >>> On 5/31/19 5:00 AM, Richard Biener wrote: On Fri, May 31, 2019 at 2:27 AM Jeff Law wrote: > > On 5/29/19 10:20 AM, Aldy Hernandez wrote: >

[PATCH][MSP430][4/4] Implement 64-bit shifts in assembly code

This patch implements 64-bit shifts in assembly code. Previously, generic C library code from libgcc would be used to perform the shifts, which was much more costly in terms of code size. I observed 700 PASS->FAIL regressions from the GCC testsuite alone when these 64-bit shifts were implemented i

[PATCH][MSP430][3/4] Disable performance optimal library code shifts when optimizing for size

This patch reduces code size by disabling the performance optimized, "const_variant" of shift library functions when optimization for size is enabled. For the following program, the below code size reduction is observed: long a; int main (void) { a = a >> 4; return 0; } With sh

[PATCH][MSP430][2/4] Emulate 16-bit shifts with rotate insn when src operand is originally in memory

This patch reduces code size by enabling the emulation of some 16-bit shift instructions with the native rotate instructions, when the source operand is in memory. This is achieved by forcing the source operand into a register. For the following program, the below code size reduction is observed:

[PATCH][MSP430][1/4] Put libgcc shift functions in their own sections

This patch reduces code size by putting each of the shift library functions from libgcc in their own section. This means that, for example, a 16-bit logical left shift does not result in code to perform a 32-bit logical left shift being included in the final executable, as the linker can now garbag

[PATCH][MSP430][0/4] Reduce code size when performing bit shifts

The following series of patches reduces the code size of MSP430 programs that make use of bit shifts. The MSP430 does not have a native instruction for shifting integers, but in some cases the native rotate instruction can be substituted. In other cases, assembly code in libgcc is used to emulate t

Re: [ARM/FDPIC v5 00/21] FDPIC ABI for ARM

Ping? On Thu, 23 May 2019 at 14:46, Christophe Lyon wrote: > > Ping? > > Any feedback other than what I got on patch 03/21 ? > > Thanks, > > Christophe > > > On 15/05/2019 14:39, Christophe Lyon wrote: > > Hello, > > > > This patch series implements the GCC contribution of the FDPIC ABI for > >

[committed] Support lastprivate(conditional:) on combined for simd

Hi! The following patch adds support for lastprivate(conditional:) on for simd. Bootstrapped/regtested on x86_64-linux and i686-linux, committed to trunk. 2019-06-04 Jakub Jelinek * gimplify.c (gimplify_scan_omp_clauses): Don't sorry_at on lastprivate conditional on combined

Re: [PATCH v2] aarch64: emit .variant_pcs for aarch64_vector_pcs symbol references

On Mon, 3 Jun 2019 at 13:28, James Greenhalgh wrote: > > On Wed, May 29, 2019 at 11:00:46AM +0100, Richard Sandiford wrote: > > Szabolcs Nagy writes: > > > v2: > > > - use aarch64_simd_decl_p to check for aarch64_vector_pcs. > > > - emit the .variant_pcs directive even for local functions. > > >

Re: [PATCH] warn on returning alloca and VLA (PR 71924, 90549)

On Mon, Jun 3, 2019 at 1:27 PM Richard Biener wrote: > > On Mon, Jun 3, 2019 at 11:37 AM Richard Biener > wrote: > > > > On Fri, May 31, 2019 at 5:35 PM Jeff Law wrote:> > > > On 5/30/19 4:56 PM, Martin Sebor wrote: > > > > On 5/30/19 10:15 AM, Jeff Law wrote: > > > >> On 5/30/19 9:34 AM, Martin

RE: [patch][aarch64]: add usra and ssra combine patterns

Hi James, I've managed to remove the odd redundant git diff change. Regarding aarch64_sra_n, this patch shouldn't affect it. I am also not aware of any way of enabling this combine inside the pattern used for those intrinsics, so I kept them separate. Cheers, Syl -Original Message- Fr

Re: undefined behavior in value_range::equiv_add()?

On Tue, Jun 4, 2019 at 12:30 AM Jeff Law wrote: > > On 6/3/19 7:13 AM, Aldy Hernandez wrote: > > On 5/31/19 5:00 AM, Richard Biener wrote: > >> On Fri, May 31, 2019 at 2:27 AM Jeff Law wrote: > >>> > >>> On 5/29/19 10:20 AM, Aldy Hernandez wrote: > On 5/29/19 12:12 PM, Jeff Law wrote: >

Re: [RFC] SHIFT_COUNT_TRUNCATED and shift_truncation_mask

>> Now, in order to get rid of the subregs in the pattern combine creates, >> I would need to be able to do something like >> >> (define_subst "subreg_subst" >> [(set (match_operand:DI 0 "" "") >> (shift:DI (match_operand:DI 1 "" "") >>(subreg:SI (match_dup:DI 2)))] >> >>

Re: [PATCH] include MEM_REF type in tree dumps (PR 90676)

On Mon, Jun 3, 2019 at 5:13 PM Martin Sebor wrote: > > On 6/3/19 4:34 AM, Richard Biener wrote: > > On Mon, Jun 3, 2019 at 10:57 AM Jakub Jelinek wrote: > >> > >> On Mon, Jun 03, 2019 at 10:36:42AM +0200, Richard Biener wrote: > To avoid this confusion the attached patch adds to the dump > >

Re: [PATCH] Mostly fix PR90726 - exponential compile-time/memory behavior

On Mon, 3 Jun 2019, Richard Biener wrote: > > This mostly fixes PR90726, employing proper visited mechanisms to > avoid exponential behavior when walking a GENERIC expression > with shared trees. It also fixes the code-generation side where > gimplification of such tree naturally explodes as wel

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

On Tue, Jun 4, 2019 at 5:21 PM Jakub Jelinek wrote: > > On Tue, Jun 04, 2019 at 05:00:05PM +0800, Hongtao Liu wrote: > > Thanks for reminding, Here is updated: > > You've missed some notes. Ok for trunk with: > 1) the following patch applied on top of your patch > 2) the ChangeLog entries moved t

[PATCH][OBVIOUS] Fix typo in tests.

Hi. One obvious patch needed after my commit to IPA ICF. Martin gcc/ChangeLog: 2019-06-04 Martin Liska * value-prof.c (dump_histogram_value): Fix typo. (gimple_mod_subtract_transform): Likewise. --- gcc/testsuite/c-c++-common/goacc/acc-icf.c | 2 +- gcc/testsuite/gfortran.

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

On Tue, Jun 04, 2019 at 05:00:05PM +0800, Hongtao Liu wrote: > Thanks for reminding, Here is updated: You've missed some notes. Ok for trunk with: 1) the following patch applied on top of your patch 2) the ChangeLog entries moved to the start of the ChangeLog (normally, ChangeLog entries are n

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

On Tue, Jun 4, 2019 at 3:59 PM Jakub Jelinek wrote: > > On Tue, Jun 04, 2019 at 03:38:08PM +0800, Hongtao Liu wrote: > > --- gcc/ChangeLog (revision 271853) > > +++ gcc/ChangeLog (working copy) > > @@ -4706,6 +4706,26 @@ > > reprocessing. Always call df_analyze before fixing up debu

New Swedish PO file for 'gcc' (version 9.1.0)

Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'gcc' has been submitted by the Swedish team of translators. The file is available at: https://translationproject.org/latest/gcc/sv.po (This file, 'gcc-9.1.0.sv.po', has jus

[PATCH 2/4] Implement N disk counters for single value and indirect call counters.

gcc/ChangeLog: 2019-06-04 Martin Liska * gcov-io.h (GCOV_DISK_SINGLE_VALUES): New. (GCOV_SINGLE_VALUE_COUNTERS): Likewise. * ipa-profile.c (ipa_profile_generate_summary): Use get_most_common_single_value. * tree-profile.c (gimple_init_gcov_profiler):

[PATCH 1/4] Remove indirect call top N counter type.

gcc/ChangeLog: 2019-06-04 Martin Liska * doc/invoke.texi: Remove param. * gcov-counter.def (GCOV_COUNTER_ICALL_TOPNV): Remove. * gcov-io.h (GCOV_ICALL_TOPN_VAL): Likewise. (GCOV_ICALL_TOPN_NCOUNTS): Likewise. * params.def (PARAM_INDIR_CALL_TOPN_

[PATCH 3/4] Dump histograms only if present.

gcc/ChangeLog: 2019-06-04 Martin Liska * value-prof.c (dump_histogram_value): Print histogram values only if present. --- gcc/value-prof.c | 72 +++- 1 file changed, 28 insertions(+), 44 deletions(-) diff --git a/gcc/value-prof.c b

[PATCH 0/4] Store multiple values for single value profilers

Hi. It's becoming more common that a training run happens in parallel environment. That can lead to a not reproducible builds caused by different order of merging of .gcda files. So that I'm suggesting to store up to 4 values for HIST_TYPE_SINGLE_VALUE and HIST_TYPE_INDIR_CALL on disk. If the cap

[PATCH 4/4] Update a bit dump format.

gcc/ChangeLog: 2019-06-04 Martin Liska * value-prof.c (dump_histogram_value): Change dump format. (gimple_mod_subtract_transform): Remove legacy comment. --- gcc/value-prof.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/gcc/value-prof.c

Re: [PATCH] Move rust_{is_mangled,demangle_sym} to a private libiberty header.

On Sat, 2019-06-01 at 17:14 +0300, Eduard-Mihai Burtescu wrote: > When libiberty/rust-demangle.c was initially added, its two exports, > rust_is_mangled and rust_demangle_sym, made it to include/demangle.h. > However, these two functions are merely implementation details of > cplus_demangle and rus

Re: [PATCH V4] Remove empty loop with assumed finiteness (PR tree-optimization/89713)

On Tue, 4 Jun 2019, Feng Xue OS wrote:  I think we should turn this option on by default, document that and note  that some languages (C++) say loops terminate. To enable this option at -O2 is not very suitable, seems to be more aggressive. Better to turn it on at -O3. Why wouldn't it be su

[PATCH] Fix PR90738

Committed to trunk. Richard. 2019-06-04 Richard Biener PR tree-optimization/90738 Revert 2019-06-03 Richard Biener * tree-ssa-sccvn.c (ao_ref_init_from_vn_reference): Get original full reference tree and record in ref->ref. (vn_reference_l

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

On Tue, Jun 04, 2019 at 03:38:08PM +0800, Hongtao Liu wrote: > --- gcc/ChangeLog (revision 271853) > +++ gcc/ChangeLog (working copy) > @@ -4706,6 +4706,26 @@ > reprocessing. Always call df_analyze before fixing up debug bind > insns. > > +2019-03-24 Hongtao Liu name

Re: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/89803)

On Mon, Jun 3, 2019 at 7:06 PM Jakub Jelinek wrote: > > On Mon, Jun 03, 2019 at 06:01:40PM +0800, Hongtao Liu wrote: > > The following patch adds forgotten avx512f fpclass instrinsics for > > masked scalar operations. > > > > Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx5

Re: [PATCH] A jump threading opportunity for condition branch

On Tue, 4 Jun 2019, Jiufu Guo wrote: > Jeff Law writes: > > > On 5/31/19 1:24 AM, Richard Biener wrote: > >> On Thu, 30 May 2019, Jeff Law wrote: > >> > >>> On 5/30/19 12:41 AM, Richard Biener wrote: > On May 29, 2019 10:18:01 PM GMT+02:00, Jeff Law wrote: > > On 5/23/19 6:11 AM, Rich