Re: [PATCH] Fix -fdebug-types-section ICE, PR91887

On 10/16/19 6:11 AM, Richard Biener wrote: The following makes sure we correctly identify a parm DIE created early in a formal parameter pack during late annotation. Bootstrapped on x86_64-unknown-linux-gnu, testing in progress. OK? OK, thanks. Jason

Re: [RFC, Darwin, PPC] Fix PR 65342.

On Sat, Oct 12, 2019 at 05:39:51PM -0500, Segher Boessenkool wrote: > On Sat, Oct 12, 2019 at 10:13:16PM +0100, Iain Sandoe wrote: > > For 32bit cases this isn't a problem since we can load/store to unaligned > > addresses using D-mode insns. > > Can you? -m32 -mpowerpc64? We did have a bug

Re: [C++ Patch] Remove most uses of in_system_header_at

On 10/16/19 11:59 AM, Paolo Carlini wrote: ... the below, slightly extended patch: 1- Makes sure the in_system_header_at calls surviving in decl.c get the same location used for the corresponding diagnostic Hmm, we probably want to change permerror to respect warn_system_headers like warning

Re: [PATCH] Fix -Wshadow=local warnings in genautomata.c

On 10/16/19 9:43 AM, Martin Sebor wrote: > On 10/16/19 9:11 AM, Richard Sandiford wrote: >> Sorry for the slow reply. >> >> Bernd Edlinger writes: >>> Hi, >>> >>> this is probably on the border to obvious. >>> >>> The REGEXP_xxx macros in genautomata are invoked >>> recursively, and the local

Re: [PATCH] Fix -Wshadow=local warnings in genautomata.c

On 10/16/19, Jakub Jelinek wrote: > On Wed, Oct 16, 2019 at 10:03:51AM -0600, Martin Sebor wrote: >> > The counter example would be: >> > #define F(x) \ >> >__extension__ (({ __typeof__ (x) _x = x; _x < 0 ? -_x : _x; })) >> > #define G(x) \ >> >__extension__ (({ __typeof__ (x) _x = x;

Re: [AArch64][SVE2] Support for EOR3 and variants of BSL

Segher Boessenkool writes: > On Wed, Oct 16, 2019 at 09:04:18PM +0100, Richard Sandiford wrote: >> Segher Boessenkool writes: >> > This isn't canonical RTL. Does combine not simplify this? >> > >> > Or, rather, it should not be what we canonicalise to: nothing is defined >> > here. >> >> But

[PATCH] [OBVIOUS] Fix old file reference in gcc/cp/cp-gimplify.c

I've found this stale reference while looking at cp-gimplify.c. tree-gimplify.c no longer exists and its contents were merged into gimple.c. Seems obvious enough. gcc/cp/ChangeLog: 2019-10-16 Luis Machado * cp-gimplify.c: Fix reference to non-existing tree-gimplify.c file.

Re: [PATCH] handle local aggregate initialization in strlen, take 2 (PR 83821)

On Mon, Oct 14, 2019 at 06:23:22PM -0600, Martin Sebor wrote: > > gcc/ChangeLog: > > PR tree-optimization/83821 > * tree-ssa-strlen.c (maybe_invalidate): Add argument. Consider > the length of a string when available. > + fprintf (dump_file, > +

[PATCH] [x86] Add detection of Icelake Client and Server

gcc/ChangeLog: * config/i386/driver-i386.c (host_detect_local_cpu): Handle icelake-client and icelake-server. * testsuite/gcc.target/i386/builtin_target.c (check_intel_cpu_model): Verify icelakes are detected correctly. libgcc/ChangeLog: *

Re: [ C++ ] [ PATCH ] [ RFC ] p1301 - [[nodiscard("should have a reason")]]

Thanks, Jason! I fixed those last things and I put the changelog below in the e-mail. I'll figure out how to write a good changelog in a commit message on the command line soon. :D 2019-10-16 JeanHeyd Meneide gcc/ * escaped_string.h: New. Refactored out of tree.c

Re: [AArch64][SVE2] Support for EOR3 and variants of BSL

On Wed, Oct 16, 2019 at 09:04:18PM +0100, Richard Sandiford wrote: > Segher Boessenkool writes: > > This isn't canonical RTL. Does combine not simplify this? > > > > Or, rather, it should not be what we canonicalise to: nothing is defined > > here. > > But when nothing is defined, let's match

Re: [PATCH][AArch64] PR79262: Adjust vector cost

Wilco Dijkstra writes: > ping > > PR79262 has been fixed for almost all AArch64 cpus, however the example is > still > vectorized in a few cases, resulting in lower performance. Increase the cost > of > vector-to-scalar moves so it is more similar to the other vector costs. As a > result >

[PATCH] RISC-V: Include more registers in SIBCALL_REGS.

This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19. This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS. It also adds the missing riscv_regno_to_class change. Tested with cross riscv32-elf and riscv64-linux toolchain build and check. There were no

Re: [ C++ ] [ PATCH ] [ RFC ] p1301 - [[nodiscard("should have a reason")]]

On 10/15/19 8:31 PM, JeanHeyd Meneide wrote: Attached is a patch for p1301 that improves in the way Jason Merrill specified earlier (https://gcc.gnu.org/ml/gcc-patches/2019-09/msg00858.html) Great, thanks! This mail is missing ChangeLog entries. My guess is that you're using git diff to

Re: [PATCH] Fix constexpr-dtor3.C FAIL on arm

On 10/16/19 12:27 PM, Jakub Jelinek wrote: > On Fri, Oct 11, 2019 at 04:14:16PM -0400, Jason Merrill wrote: >>> On x86_64 and most other targets, cleanup here (if non-NULL) is the >>> CALL_EXPR, as destructor return type is void, but on arm, as the dtor return >>> type is some pointer, the

Re: [PATCH] Fix constexpr-dtor3.C FAIL on arm

On 10/16/19 12:27 PM, Jakub Jelinek wrote: On Fri, Oct 11, 2019 at 04:14:16PM -0400, Jason Merrill wrote: On x86_64 and most other targets, cleanup here (if non-NULL) is the CALL_EXPR, as destructor return type is void, but on arm, as the dtor return type is some pointer, the CALL_EXPR is

Re: [PATCH] Help compiler detect invalid code

Here is a version with __detail::__copy and __detail::__copy_backward. I prefered to introduce the __detail namespace cause __copy is quite a common name so putting it in __detail namespace will I hope clarify that it is for internal usage only. I even hesitated to put more details into this

Re: [AArch64][SVE2] Support for EOR3 and variants of BSL

Segher Boessenkool writes: > Hi, > > [ Please don't use application/octet-stream attachments. Thanks! ] > > On Wed, Oct 16, 2019 at 04:24:29PM +, Yuliang Wang wrote: >> +;; Unpredicated bitwise select. >> +(define_insn "*aarch64_sve2_bsl" >> + [(set (match_operand:SVE_I 0 "register_operand"

Re: [AArch64][SVE2] Support for EOR3 and variants of BSL

Thanks for the patch, looks really good. Yuliang Wang writes: > +;; Use NBSL for vector NOR. > +(define_insn_and_rewrite "*aarch64_sve2_nor" > + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?") > + (unspec:SVE_I > + [(match_operand 3) > +(and:SVE_I > +

Re: [PATCH] Fix -Wshadow=local warnings in genautomata.c

On Wed, Oct 16, 2019 at 10:03:51AM -0600, Martin Sebor wrote: > PS The counterexample nicely illustrates why -Wself-init should > be in -Wall like in Clang or MSVC, or at least in -Wextra like in > ICC. Let me take it as a reminder to submit a patch for GCC 10. c-family/c-gimplify.c says:

[PATCH] [og9] Re-do OpenACC private variable resolution

This patch (for the openacc-gcc-9-branch) reworks how the partitioning level for OpenACC "private" variables is calculated and represented in the compiler. There have been two previous approaches: - The first (by Chung-Lin Tang) recorded which variables should be made private per-gang in each

[PATCH] [og9] Fix libgomp serial-dims.c test for AMD GCN

This patch adds support for AMD GCN offloading to the libgomp.oacc-c-c++-common/serial-dims.c test case. I will apply to the og9 branch shortly. Thanks, Julian ChangeLog libgomp/ * testsuite/libgomp.oacc-c-c++-common/serial-dims.c: Support AMD GCN. ---

Re: [AArch64][SVE2] Support for EOR3 and variants of BSL

Hi, [ Please don't use application/octet-stream attachments. Thanks! ] On Wed, Oct 16, 2019 at 04:24:29PM +, Yuliang Wang wrote: > +;; Unpredicated bitwise select. > +(define_insn "*aarch64_sve2_bsl" > + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?") > + (xor:SVE_I > +

Re: [ C++ ] [ PATCH ] [ RFC ] p1301 - [[nodiscard("should have a reason")]]

Dear Dave, Thanks for sharing all of that! It was very helpful to read it over again, and it was helpful in IRC yesterday. As a bit of a "that was strange" moment, I ran the builds again and did NOT do --disable-bootstrap with the patch on a different machine. They built and ran fine,

[PATCH] Communicate lto-wrapper and ld through a file

Hi, Previously, the lto-wrapper communicates with ld by creating a pipe from lto-wrapper's stdout to ld's stdin. This patch uses a temporary file for this communication, releasing stdout to be used for debugging. I've run a full testsuite and bootstrapped LTO in a linux x86_64, and found no

Re: [gomp4.1] Start of structure element mapping support

On Wed, Oct 16, 2019 at 03:22:52PM +0200, Thomas Schwinge wrote: > Stumbled over this while reviewing Julian's "Factor out duplicate code in > gimplify_scan_omp_clauses": > ..., which here gets writte to... > > > + if (base != decl) > > + break; > >

Re: [PATCH] Fix -Wshadow=local warnings in genautomata.c

On Wed, Oct 16, 2019 at 10:03:51AM -0600, Martin Sebor wrote: > > The counter example would be: > > #define F(x) \ > >__extension__ (({ __typeof__ (x) _x = x; _x < 0 ? -_x : _x; })) > > #define G(x) \ > >__extension__ (({ __typeof__ (x) _x = x; F(_x); })) > > where a -Wshadow diagnostics

[arm] fix bootstrap failure due to uninitialized warning

The Arm port is failing bootstrap because GCC is now warning about an unitialized array. The code is complex enough that I certainly can't be sure the compiler is wrong, so perhaps the best fix here is just to memset the entire array before use. * config/arm/arm.c

Re: [PATCH] Fix -Wshadow=local warnings in genautomata.c

On Wed, 16 Oct 2019, Jakub Jelinek wrote: > The counter example would be: > #define F(x) \ > __extension__ (({ __typeof__ (x) _x = x; _x < 0 ? -_x : _x; })) > #define G(x) \ > __extension__ (({ __typeof__ (x) _x = x; F(_x); })) > where a -Wshadow diagnostics could point the author at a

Re: [PATCH] Fix constexpr-dtor3.C FAIL on arm

On Fri, Oct 11, 2019 at 04:14:16PM -0400, Jason Merrill wrote: > > On x86_64 and most other targets, cleanup here (if non-NULL) is the > > CALL_EXPR, as destructor return type is void, but on arm, as the dtor return > > type is some pointer, the CALL_EXPR is wrapped into a NOP_EXPR to void. > >

[AArch64][SVE2] Support for EOR3 and variants of BSL

Hi, This patch adds combine pass support for the following SVE2 bitwise logic instructions: - EOR3 (3-way vector exclusive OR) - BSL (bitwise select) - NBSL (inverted ") - BSL1N (" with first input inverted) - BSL2N (" with second input inverted)

Re: [PATCH][AArch64] Set SLOW_BYTE_ACCESS

On 11/10/2019 00:08, Ramana Radhakrishnan wrote: On Thu, Oct 10, 2019 at 7:06 PM Richard Sandiford wrote: Wilco Dijkstra writes: ping Contrary to all documentation, SLOW_BYTE_ACCESS simply means accessing bitfields by their declared type, which results in better codegeneration on

[wwwdocs, committed] Fix GCC 8.2 release date (was: wwwdocs/htdocs/gcc-8 index.html)

Hi! On 2018-07-26T11:56:36+, ja...@gcc.gnu.org wrote: > Files modified in the GCC repository. Log entry: > > Fix up a typo in the release year. ..., but the day also needs to be fixed. ;-) Pushed to wwwdocs the attached commit 0dd4c6860fe284cef2df33ec98b2754c25d10438 "Fix GCC 8.2 release

Re: [PATCH] Fix -Wshadow=local warnings in genautomata.c

On 10/16/19 9:50 AM, Jakub Jelinek wrote: On Wed, Oct 16, 2019 at 09:43:49AM -0600, Martin Sebor wrote: Should the warning trigger when the shadowing name results from macro expansion? The author of a macro can't (in general) know what context it's going to be used, and when different macros

Re: [C++ Patch] Remove most uses of in_system_header_at

... the below, slightly extended patch: 1- Makes sure the in_system_header_at calls surviving in decl.c get the same location used for the corresponding diagnostic; exploit locations[ds_typedef] in an error_at in grokdeclarator. Tested, as usual, on x86_64-linux. Thanks, Paolo.

Re: [PATCH] Fix -Wshadow=local warnings in genautomata.c

On Wed, Oct 16, 2019 at 09:43:49AM -0600, Martin Sebor wrote: > Should the warning trigger when the shadowing name results from > macro expansion? The author of a macro can't (in general) know > what context it's going to be used, and when different macros > come from two different third party

Re: [PATCH] Fix -Wshadow=local warnings in genautomata.c

On 10/16/19 9:11 AM, Richard Sandiford wrote: Sorry for the slow reply. Bernd Edlinger writes: Hi, this is probably on the border to obvious. The REGEXP_xxx macros in genautomata are invoked recursively, and the local values are all named _regexp and shadow each other. Fixed by using

Re: [PATCH][ARM] Switch to default sched pressure algorithm

On 16/10/2019 13:13, Wilco Dijkstra wrote: Hi Christophe, I've noticed that your patch caused a regression: FAIL: gcc.dg/tree-prof/pr77698.c scan-rtl-dump-times alignments "internal loop alignment added" 1 That's just a testism - it only tests for loop alignment and doesn't consider the

Re: [PATCH] [MIPS] Remove unnecessary moves around dpadd and dpsub

On 10/16/19 9:03 AM, Mihailo Stojanovic wrote: > Unnecessary moves around dpadd and dpsub are caused by different pseudos > being assigned to the input-output operands which correspond to the same > register. > > This forces the same pseudo to the input-output operands, which removes > unnecesary

Re: [PATCH] Fix -Wshadow=local warnings in genautomata.c

Sorry for the slow reply. Bernd Edlinger writes: > Hi, > > this is probably on the border to obvious. > > The REGEXP_xxx macros in genautomata are invoked > recursively, and the local values are all named _regexp > and shadow each other. > > > Fixed by using different names _regexp1..6 for each

Re: [PATCH] handle local aggregate initialization in strlen, take 2 (PR 83821)

On 10/14/19 6:23 PM, Martin Sebor wrote: > When a subsequent element or member of a local aggregate containing > a prior character array is initialized the strlen pass discards > the length it computed for the prior element/member.  E.g., here: > >   struct { char a[4], b[4]; } s = { "1", "12" };

Re: [PATCH] handle string copies with non-constant lengths (PR 91996)

On 10/15/19 3:24 PM, Martin Sebor wrote: > The attached patch removes a FIXME added recently to the strlen > pass as a reminder to extend the handling of multi-byte stores > of characters copied from non-constant strings with constant > lengths to strings with non-constant lengths in some known 

[PATCH] i386: Add clear_ratio to processor_costs

i386.h has #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) It is impossible to have CLEAR_RATIO > 6. This patch adds clear_ratio to processor_costs, sets it to the minimum of 6 and move_ratio in all cost models and defines CLEAR_RATIO with clear_ratio. *

[PATCH] [MIPS] Remove unnecessary moves around dpadd and dpsub

Unnecessary moves around dpadd and dpsub are caused by different pseudos being assigned to the input-output operands which correspond to the same register. This forces the same pseudo to the input-output operands, which removes unnecesary moves. Tested on mips-mti-linux-gnu. gcc/ChangeLog:

Re: [PATCH] find_partition_fixes: remove unused bbs_in_cold_partition variable

On 10/16/19 8:26 AM, Ilya Leoshkevich wrote: > Bootstrapped and regtested on x86_64-redhat-linux. > I noticed this while looking into PR92007. > > gcc/ChangeLog: > > 2019-10-16 Ilya Leoshkevich > > * cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition. OK. Thanks, Jeff

[PATCH] V6, #17 of 17: Add stack protection test

This is a new test for the stack protection code that was added in V6 patch #4. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test suite. I have built both Spec 2006 and Spec 2017 with all of these patches installed

[PATCH] V6, #16 of 17: Wrong subject, should have been update @pcrel

Note, patch #16 had the wrong subject line. It should have been that modifies @pcrel to use an explicit (0),1. Sorry about that. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V6, #16 of 17: New test for stack protection

This patch adds an explicit (0),1 to labels used with the @pcrel syntax. The intention is make sure that the user does not use an instruction that assumes PC-relative instructions can take a base register (as I did in the V4 patches). This was V5 patch #15. This patch is optional. If it is not

[PATCH] V6, #15 of 17: Add PC-relative tests

This patch adds PC-relative tests for the various types, and verifies that expected instructions are generated. This is the same as V5 patch #14. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test suite. I have built

Re: [PATCH 3/4] Factor out duplicate code in gimplify_scan_omp_clauses

Hi Julian! On 2019-10-06T15:32:36-0700, Julian Brown wrote: > This patch factors out some code in gimplify_scan_omp_clauses into two > new outlined functions. Yay for such simplification, and yay for documenting what's going on! > Previously approved here: > >

[PATCH] V6, #14 of 17: Add prefixed load/store tests with large offsets

This patch adds a bunch of tests for each of the types to verify that it generates the appropriate instructions for addresses that do not fit in a 16-bit offset. This patch is essentially V5 patch #13. Along with the other patches, I have done bootstraps on a little endian power8 system, and

[PATCH] V6, #13 of 17: Add test for prefix pre-modify

This patch adds a test to make sure the GCC compiler does not try to issue a pre-modify prefixed address load/store since the prefixed instructions do not support an update form. This patch was in V5 patch #12 but it was split out. Along with the other patches, I have done bootstraps on a little

[PATCH] V6, #12 of 17: Add prefix test for DS/DQ instructions

This patch adds a new test that makes sure the appropriate prefixed instruction is generated if a memory is attempted for DS-format or DQ-format instructions where the offset does not fit the DS or DQ constraints. This patch was in V5 patch #12 and was split out in this patch. Along with the

[PATCH] find_partition_fixes: remove unused bbs_in_cold_partition variable

Bootstrapped and regtested on x86_64-redhat-linux. I noticed this while looking into PR92007. gcc/ChangeLog: 2019-10-16 Ilya Leoshkevich * cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition. --- gcc/cfgrtl.c | 2 -- 1 file changed, 2 deletions(-) diff --git

[PATCH] V6, #11 of 17: Add PADDI tests

This patch adds 3 tests for the PADDI instruction. This was originally part of V5 patch #12, but it was split out. 2019-10-15 Michael Meissner * gcc.target/powerpc/paddi-1.c: New test to test using PLI to load up a large DImode constant. *

[PATCH] V6, #10 of 17: Update target-supports.exp

This patch adds 2 new target supports options for the testsuite. One is for whether prefixed instructins with 34-bit offsets are supported. The other is whether PC-relative instructions are supported. This was originally part of V5 patch #12, but it was split out to be a separate patch. Along

[PATCH] V6, #9 of 17: Change defaults on Linux 64-bit to enable -mpcrel

This patch changes the default for Linux 64-bit to enable -mpcrel and -mprefixed-addr by default when you use -mcpu=future. Other OS targets do not enable these switches by default. This is the same as V5 patch #11. Along with the other patches, I have done bootstraps on a little endian power8

[PATCH] V6, #8 of 17: Use PADDI to add 34-bit constants

This patch uses the PADDI instruction to add 34-bit constants that can't be done with a single ADDI or ADDIS instruction. This patch is the same as V5 patch #10. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test

[PATCH] V6, #7 of 17: Use PADDI/PLI to load up 32-bit SImode constants

This patch uses PADDI (PLI) to load up 32-bit SImode constants that can't be loaded with either a single ADDI or ADDIS instruction. This patch is the same as V5 patch #9. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the

[PATCH] V6, #6 of 17: Use PADDI/PLI to load up 34-bit DImode constants

This patch uses PADDI (PLI) to load up 34-bit DImode constants. This is the same patch as V5 patch #8. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test suite. I have built both Spec 2006 and Spec 2017 with all of

[PATCH] V6, #5 of 17: Add prefixed instruction support to vector extract optimizations

This patch updates the support for optimizing vector extracts to know about prefixed addressing. There are two parts to the patch: 1) If a vector extract with a constant element number extracts an element from a vector residing in memory that uses a prefixed address (either numeric or

Re: [PATCH V2] rs6000: -flto forgets 'no-vsx' function attributes (PR target/70010)

Segher Boessenkool writes: > Hi! > >> the callee explicitly disables some isa_flags the caller is using. > > No trailing spaces please. Updated. > >> + /* The callee's options must be a subset of the caller's options, i.e. >> + a vsx function may inline an altivec function, but a

[PATCH] V6, #4 of 17: Add prefixed instruction support to stack protect insns

This patch fixes the stack protection insns to support stacks larger than 16-bits on the 'future' system using prefixed loads and stores. This rewrites V5 patch #5. In earlier patches, I had had a variant of this patch, but I was asked to restrict the protect insns to use non-prefixed insns,

[PATCH] V6, #3 of 17: Update lwa_operand for prefixed PLWA

This patch allows using load SImode with sign extend to DImode to generate the PLWA instruction on the 'future' machine if the offset for the load has the bottom 2 bits being non-zero. The normal LWA instruction is a DS format instruction, and it needs the bottom 2 bits to be 0. This patch was

[PATCH] V6, #2 of 17: Minor code reformat

This patch tweaks the code formatting that I noticed in making the previous patch for some of the 128-bit mode move instructions. Originally this was part of V5 patch #2, but it has been moved to a separate patch. Along with the other patches, I have done bootstraps on a little endian power8

[PATCH] V6, #1 of 17: Use ADJUST_INSN_LENGTH for prefixed instructions

This patch uses the target hook ADJUST_INSN_LENGTH to change the length of instructions that contain prefixed memory/add instructions. There are 2 new insn attributes: 1) num_insns: If non-zero, returns the number of machine instructions in an insn. This simplifies the calculations in

Re: [gomp4.1] Start of structure element mapping support

Hi Jakub! Stumbled over this while reviewing Julian's "Factor out duplicate code in gimplify_scan_omp_clauses": On 2015-07-31T18:16:10+0200, Jakub Jelinek wrote: > This patch is the start of implementation of struct element mapping. Not quite the same, but similar code is still present in GCC

[PATCH] Relax integer condition reduction, simplify vect_is_simple_reduction

It happens we cannot have different typed data and index for integer condition reductions right now, for whatever reason. The following makes that work, even for double data and integer index. There's hope this enables some relevant amount of extra vectorization. Actually this is fallout from

Re: [ C++ ] [ PATCH ] [ RFC ] p1301 - [[nodiscard("should have a reason")]]

On Tue, 2019-10-15 at 20:31 -0400, JeanHeyd Meneide wrote: > Attached is a patch for p1301 that improves in the way Jason Merrill > specified earlier > (https://gcc.gnu.org/ml/gcc-patches/2019-09/msg00858.html), but it > keeps segfaulting on my build of GCC. I don't know what changes I've > made

PowerPC future machine patches, version 6

This is version 6 of the patches for the PowerPC 'future' machine. There are currently 17 patches in this series. Compared to the V5 patches, the following changes have been made: 1) The length calculation for memory references involving prefixed addresses has been moved to the target hook

Re: [PATCH][ARM] Switch to default sched pressure algorithm

Hi Christophe, > I've noticed that your patch caused a regression: > FAIL: gcc.dg/tree-prof/pr77698.c scan-rtl-dump-times alignments > "internal loop alignment added" 1 That's just a testism - it only tests for loop alignment and doesn't consider the possibility of the loop being jumped into

Re: [SVE] PR86753

Richard Biener writes: > On Tue, Oct 15, 2019 at 8:07 AM Prathamesh Kulkarni > wrote: >> >> On Wed, 9 Oct 2019 at 08:14, Prathamesh Kulkarni >> wrote: >> > >> > On Tue, 8 Oct 2019 at 13:21, Richard Sandiford >> > wrote: >> > > >> > > Leaving the main review to Richard, just some comments... >>

Re: Add expr_callee_abi

Richard Biener writes: > On October 14, 2019 2:53:36 PM GMT+02:00, Richard Sandiford > wrote: >>Richard Biener writes: >>> On Fri, Oct 11, 2019 at 4:39 PM Richard Sandiford >>> wrote: This turned out to be useful for the SVE PCS support, and is a >>natural tree-level analogue

[committed][AArch64] Add partial SVE vector modes

This patch adds extra vector modes that represent a half, quarter or eighth of what an SVE vector can hold. This is useful for describing the memory vector involved in an extending load or truncating store. It might also be useful in future for representing "unpacked" SVE registers, i.e.

[committed][AArch64] Improve poly_int handling in aarch64_layout_frame

I'd used known_lt when converting these conditions to poly_int, but on reflection that was a bad choice. The code isn't just doing a range check; it specifically needs constants that will fit in a certain encoding. Tested on aarch64-linux-gnu and aarch64_be-elf, applied as r277061. Richard

[committed][AArch64] Add an assert to aarch64_layout_frame

This patch adds an assert that all the individual *_adjust allocations add up to the full frame size. With that safety net, it seemed slightly clearer to use crtl->outgoing_args_size as the final adjustment where appropriate, to match what's used in the comments. This is a bit overkill on its

[committed][AArch64] Use frame reference in aarch64_layout_frame

Using the full path "cfun->machine->frame" in aarch64_layout_frame led to awkward formatting in some follow-on patches, so it seemed worth using a local reference instead. Tested on aarch64-linux-gnu and aarch64_be-elf, applied as r277059. Richard 2019-10-16 Richard Sandiford gcc/

Re: [PATCH] Use __is_same_as for std::is_same and std::is_same_v

On 16/10/19 10:43 +0100, Jonathan Wakely wrote: On 16/10/19 10:42 +0100, Jonathan Wakely wrote: On 12/10/19 18:15 +0200, Romain Geissler wrote: Le sam. 12 oct. 2019 à 17:44, Romain Geissler a écrit : It looks like this creates the following error when I try to bootstrap clang 9.0.0 using

[PATCH] Fix -fdebug-types-section ICE, PR91887

The following makes sure we correctly identify a parm DIE created early in a formal parameter pack during late annotation. Bootstrapped on x86_64-unknown-linux-gnu, testing in progress. OK? Thanks, Richard. 2019-10-16 Richard Biener PR debug/91887 * dwarf2out.c

[PATCH] Fix PR92119

Committed as obvious. Richard. 2019-10-16 Richard Biener PR tree-optimization/92119 * tree-vect-patterns.c (vect_recog_rotate_pattern): Guard against missing bswap lhs. Index: gcc/tree-vect-patterns.c

Re: [PATCH V2] rs6000: -flto forgets 'no-vsx' function attributes (PR target/70010)

Hi! On Wed, Oct 16, 2019 at 04:50:21PM +0800, Jiufu Guo wrote: > In PR70010, a function is marked with target(no-vsx) to disable VSX code > generation. To avoid VSX code generation, this function should not be > inlined into VSX function. > > In previous implementation, target of non-vsx is

Re: [PATCH] Use __is_same_as for std::is_same and std::is_same_v

On 16/10/19 10:42 +0100, Jonathan Wakely wrote: On 12/10/19 18:15 +0200, Romain Geissler wrote: Le sam. 12 oct. 2019 à 17:44, Romain Geissler a écrit : It looks like this creates the following error when I try to bootstrap clang 9.0.0 using the latest gcc and libstdc++ from trunk. Note that

Re: [PATCH] Use __is_same_as for std::is_same and std::is_same_v

On 12/10/19 18:15 +0200, Romain Geissler wrote: Le sam. 12 oct. 2019 à 17:44, Romain Geissler a écrit : It looks like this creates the following error when I try to bootstrap clang 9.0.0 using the latest gcc and libstdc++ from trunk. Note that with g++, there is no problem, however it looks

Re: [PATCH] Fix PR91975, tame PRE some more

On Mon, 7 Oct 2019, Richard Biener wrote: > > The following tries to address the issue that PRE is quite happy > to introduce new IVs in loops just because it can compute some > constant value on the loop entry edge. In principle there's > already code that should work against that but it

Re: [PATCH 2/4] Use gomp_map_val for OpenACC host-to-device address translation

Hi! On 2019-10-06T15:32:35-0700, Julian Brown wrote: > This patch uses gomp_map_val for OpenACC host-to-device address > translation instead of open-coding the device address calculation. (As has been discussed before.) (And then, also see "'GOACC_parallel_keyed'

Re: [PATCH] OpenACC reference count consistency checking

Hi! On 2019-10-03T09:35:05-0700, Julian Brown wrote: > This patch provides self-checking for consistency of the OpenACC > reference-counting implementation in libgomp. Earlier submissions included description what exactly this is doing,

[PATCH V2] rs6000: -flto forgets 'no-vsx' function attributes (PR target/70010)

Hi, In PR70010, a function is marked with target(no-vsx) to disable VSX code generation. To avoid VSX code generation, this function should not be inlined into VSX function. In previous implementation, target of non-vsx is treated as subset target with vsx, even user set no-vsx attribute.

Re: [PATCH][AArch64] Fix symbol offset limit

Wilco Dijkstra writes: > Hi Richard, >> Sure, the "extern array of unknown size" case isn't about section anchors. >> But this part of my message (snipped above) was about the other case >> (objects of known size), and applied to individual objects as well as >> section anchors. >> >> What I was

Re: [PATCH V4] Extend IPA-CP to support arithmetically-computed value-passing on by-ref argument (PR ipa/91682)

Hi Philipp, This patch is still under code review, might still need some time. Thanks, Feng From: Philipp Tomsich Sent: Wednesday, October 16, 2019 12:05 AM To: Feng Xue OS Cc: Martin Jambor; Jan Hubicka; gcc-patches@gcc.gnu.org; Christoph Müllner;

Re: [patch] canonicalize unsigned [1,MAX] ranges into ~[0,0]

On Wed, Oct 16, 2019 at 03:38:38AM -0400, Aldy Hernandez wrote: > Would you take care of this, or shall I? Will defer to you, I have quite a lot of stuff on my plate ATM. Jakub

Re: [patch] canonicalize unsigned [1,MAX] ranges into ~[0,0]

On 10/15/19 2:16 PM, Jakub Jelinek wrote: On Tue, Oct 15, 2019 at 08:35:07AM -0400, Aldy Hernandez wrote: I'm seeing this on 32-bit i386-pc-solaris2.11 and sparc-sun-solaris2.11, with more reports for armv8l, pru, and s390x. Comparing the dumps between 64 and 32-bit, I see -_1: int * [1B,