>
> The same thing ought to work for smov, so it would be good to do both.
> That would also make the split between the original and new patterns more
> obvious: left shift for the old pattern, right shift for the new pattern.
>
Done, though because umov can do multilevel extensions I couldn't
> > This moves the pattern detection to match.pd instead.
>
> where's the other copy and is it possible to remove it with this patch?
>
It looks like it's spread over various passes. Starting with forwardprop.
>
> > + (simplify
> > + (bit_ior:c
> > + (mult:c @0 (convert (convert2? (op@4 @2
Hi,
This is a cleaned up version addressing all feedback.
Bootstrapped Regtested on aarch64-none-linux-gnu,
x86_64-pc-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* match.pd: Add new rule.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/if-compare_1.c:
Hi All,
This is a respin with all feedback addressed.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* match.pd: Add fneg/fadd rule.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/simd/addsub_1.c: New test.
Ping
> -Original Message-
> From: Gcc-patches bounces+tamar.christina=arm@gcc.gnu.org> On Behalf Of Tamar
> Christina via Gcc-patches
> Sent: Friday, September 23, 2022 10:34 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; nd ;
> Richard Sandiford ; Marcus Shawcroft
>
>
Hi All,
Ping, and updated patch based on mid-end changes.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (@aarch64_bitmask_udiv3): New.
* config/aarch64/aarch64.cc
Ping
> -Original Message-
> From: Tamar Christina
> Sent: Friday, September 23, 2022 10:34 AM
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
> ; Richard Sandiford
>
> Subject: [PATCH 3/4]AArch64 Add SVE2 implementation for pow2 bitmask
>
>
> The type of the expression should be available via the mode and the
> signedness, no? So maybe to avoid having both RTX and TREE on the target
> hook pass it a wide_int instead for the divisor?
>
Done.
Bootstrapped Regtested on aarch64-none-linux-gnu, x86_64-pc-linux-gnu
and no issues.
As $subject. Pushed to trunk.
Regards,
Ramana
diff --git a/MAINTAINERS b/MAINTAINERS
index e4e7349a6d9..55c5ef95806 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -60,7 +60,7 @@ arc port Joern Rennecke
arc port Claudiu Zissulescu
arm port
Hello,
thanks for checking the performance. The patch is OK.
Honza
On Mon, Oct 31, 2022 at 11:39 AM Joshi, Tejas Sanjay <
tejassanjay.jo...@amd.com> wrote:
> [Public]
>
> Hi,
>
> > It is not latency. It is reciprocal throughput. For example, the
> multiplication instruction has
> > latency 3
[Public]
Hi,
> It is not latency. It is reciprocal throughput. For example, the
> multiplication instruction has
> latency 3 and reciprocal throughput 1, and the corresponding execution unit
> can accept a new
> multiplication instruction each cycle. In the .md file we are modeling that
> by
On Fri, 21 Oct 2022 at 16:58, Jakub Jelinek wrote:
>
> Hi!
>
> The following patch adds support for extended floating point
> types.
> C++23 removes the float/double/long double specializations from the spec
> and instead adds explicit(bool) specifier on the converting constructor.
> The patch
On Fri, 21 Oct 2022 at 08:29, Jakub Jelinek wrote:
>
> Hi!
>
> The following patch isn't for immediate commit, as it has several
> dependencies, in particular:
> https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603665.html
> https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604080.html
Le 30/10/2022 à 22:25, Mikael Morin a écrit :
Le 30/10/2022 à 20:23, Mikael Morin a écrit :
Another probable issue is your change to create_function_arglist
changes arglist/hidden_arglist without also changing
typelist/hidden_typelist accordingly. I think a change to
gfc_get_function_type is
Prathamesh Kulkarni writes:
> On Wed, 26 Oct 2022 at 21:07, Richard Sandiford
> wrote:
>>
>> Sorry for the slow response. I wanted to find some time to think
>> about this a bit more.
>>
>> Prathamesh Kulkarni writes:
>> > On Fri, 30 Sept 2022 at 21:38, Richard Sandiford
>> > wrote:
>> >>
>>
On Mon, Oct 31, 2022 at 2:25 AM liuhongt wrote:
>
> This patch doens't handle variable count since it require 5 insns to
> be combined to get wanted pattern, but current pass_combine only
> supports at most 4.
> This patch doesn't handle 16-bit shrd/shld either.
>
> Ideally, we can avoid
Pushed to r13-3571.
在 2022/10/29 下午2:53, Lulu Cheng 写道:
v1 - > v2:
1. When the macro __loongarch_lp64 is defined, the VTV_PAGE_SIZE is set to 64K.
2. In the vtv_malloc.cc file __vtv_malloc_init function, it does not check
whether VTV_PAGE_SIZE is equal to the system page size, if the macro
On Mon, Oct 31, 2022 at 2:10 AM liuhongt wrote:
>
> >You have a couple of other patterns where operand 1 is matched to
> >produce vmovddup insn. These are *avx512f_unpcklpd512 and
> >avx_unpcklpd256. You can also remove expander in both
> >cases.
>
> Yes, changed in V2 patch.
>
> Bootstrapped and
> could you please refresh/recheck your patch for the current gcc master
> and solve the objections noted in the thread? is it possible?
I have attached a revised version of the original patch at:
https://gcc.gnu.org/legacy-ml/gcc-patches/2019-06/msg01840.html
This reimplements the GNU threads
Ping ping
On Mon, Oct 24, 2022, 08:04 Aldy Hernandez wrote:
> PING
>
> On Mon, Oct 17, 2022 at 8:21 AM Aldy Hernandez wrote:
> >
> > On Thu, Oct 13, 2022 at 7:57 PM Jakub Jelinek wrote:
> > >
> > > On Thu, Oct 13, 2022 at 02:36:49PM +0200, Aldy Hernandez wrote:
> > > > +// Like
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