On Mon, 17 Apr 2023, Richard Biener wrote:
> On Fri, 14 Apr 2023, Hans-Peter Nilsson wrote:
> > If after all, a change to the size of the code and mode
> > bit-fields in rtx_def is necessary, like to still fit 64 bytes
(Sorry: 64 bits, not counting the union u.)
> > such become non-byte sizes
Hi Kewen,
On 2023-04-19 10:53, Kewen.Lin wrote:
Hi Jeff,
on 2023/4/19 10:03, Jiufu Guo wrote:
Hi,
On P7, option -mno-allow-movmisalign is added during testing, which
prevents slp happen on the case.
Like Like PR65484 and PR87306, this patch use vect_hw_misalig to guard
Dup like...
This is primarily Raphael's work. All I did was adjust it to apply to
the trunk and add the new types to generic.md's scheduling model.
The basic idea here is to make sure we have the ability to schedule the
bitmanip instructions with a finer degree of control. Some of the
bitmanip
Use swap_communattive_operands_p for canonicalization. When both value
has same operand precedence value, then first bit in the mask should
select first operand.
The canonicalization should help backends for pattern match. .i.e. x86
backend has lots of vec_merge patterns, combine will create any
On Thu, Apr 20, 2023 at 10:56 AM juzhe.zh...@rivai.ai
wrote:
>
> >> The comment above might not sync with your implementation?
> Address comment.
>
> >> Actually, you've allowed TARGET_MIN_VLEN < 128 && riscv_autovec_lmul <
> >> RVV_M2
> Not sure I am on the same page with you. I return
> Date: Wed, 19 Apr 2023 22:16:36 +0200
> From: Bernhard Reutner-Fischer
> On 19 April 2023 21:21:18 CEST, Bernhard Reutner-Fischer
> wrote:
> >Hi H-P!
> >
> >This begs the question iff now (i fear it's not), upon
> >successful match(es), the whole peepholes get re-run
> >again per BB (ATM?),
>> The comment above might not sync with your implementation?
Address comment.
>> Actually, you've allowed TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2
Not sure I am on the same page with you. I return word_mode for this situation,
the auto-vectorization
will be disabled. I have testcase
> +/* Return the vectorization machine mode for RVV according to LMUL. */
> +machine_mode
> +preferred_simd_mode (scalar_mode mode)
> +{
> + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128
> + which is -march=rv64gcv. Since GCC loop vectorizer report ICE
> + when we
1. We should only support len_load/len_store in the first patch before any
other auto-vectorization operation.
I have sent the patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616223.html
2. cond_ is the conditional auto-vectorization pattern used by
reduction operation and
All functions should be dropped except "riscv_vector_preferred_simd_mode".
I known you take from "rvv-next". However, the implementation of
"prefer_simd_mode" in "rvv-next" is incorrect.
The most important part of implementing this function is that we should
gurantee compiler will not generate
Hi, Michael. Thanks for extracting patches from "rvv-next". I have several
comments here:
1. I think it's not appropriate and useless to support such many target hook in
the first auto-vec support patch.
You should only support TARGET_VECTORIZE_PREFERRED_SIMD_MODE is enough,
supporting too
On Linux/x86_64,
ed32ec26697cc77492d094b31a0d2eebc0535644 is the first bad commit
commit ed32ec26697cc77492d094b31a0d2eebc0535644
Author: Jason Merrill
Date: Tue Apr 18 17:12:17 2023 -0400
c++: fix 'unsigned __int128_t' semantics [PR108099]
caused
FAIL: g++.dg/ext/int128-8.C
On Thu, Apr 20, 2023 at 8:46 AM liuhongt wrote:
>
> 1547 /* If this insn loads a parameter from its stack slot, then it
> 1548 represents a savings, rather than a cost, if the parameter is
> 1549 stored in memory. Record this fact.
> 1550
> 1551 Similarly if we're loading other
This small patch just changes around the code slightly to
make it easier to understand that the cases were handling diamond
shaped BB for both do_store_elim/do_hoist_loads.
There is no effect on code output at all since all of the checks
are the same still.
Note this depends on
After optimization for RA, memory op is not propagated into
instructions(>1), and it make testcases not generate vxorps since
the memory is loaded into the dest, and the dest is never unused now.
So rewrite testcases to make the codegen more stable.
gcc/testsuite/ChangeLog:
*
1547 /* If this insn loads a parameter from its stack slot, then it
1548 represents a savings, rather than a cost, if the parameter is
1549 stored in memory. Record this fact.
1550
1551 Similarly if we're loading other constants from memory (constant
1552 pool, TOC references,
On 4/19/23 12:03, Ajit Agarwal wrote:
Hello All:
This is patch-4 to improve ree pass for rs6000 target.
Use ABI interfaces support.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
ree: Improve ree pass for rs6000 target.
For rs6000 target we see
Hi, Richards.
Since GCC 14 is open and this patch has been boostraped && tested on X86.
Is this patch supporting variable IV OK for the trunk ?
Thanks
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-04-07 09:47
To: gcc-patches
CC: richard.sandiford; rguenther; jeffreyalaw; Juzhe-Zhong
On 4/19/23 12:00, Ajit Agarwal wrote:
Hello All:
This is patch-3 to improve ree pass for rs6000 target.
Main functionality routines to imprve ree pass.
Bootstrapped and regtested on powerpc64-gnu-linux.
Thanks & Regards
Ajit
ree: Improve ree pass for rs6000 target.
For
On 19 April 2023 09:06:28 CEST, Lipeng Zhu via Fortran
wrote:
>This patch try to introduce the rwlock and split the read/write to
>unit_root tree and unit_cache with rwlock instead of the mutex to
>increase CPU efficiency. In the get_gfc_unit function, the percentage
>to step into the
For diamond bb phi node detection, there is a check
to make sure bb1 is not empty. But in the case where
bb1 is empty except for a predicate, empty_block_p
will still return true but the minmax code handles
that case already so there is no reason to check
if the basic block is empty.
This patch
[+list]
On 19 April 2023 21:21:18 CEST, Bernhard Reutner-Fischer
wrote:
>Hi H-P!
>
>This begs the question iff now (i fear it's not), upon successful match(es),
>the whole peepholes get re-run again per BB (ATM?), exposing more
>opportunities?
>If not, would we want to retry, at least for
Hi!
The subject should be something like
rs6000: Enable REE pass by default
(and no period at the end).
On Wed, Apr 19, 2023 at 11:23:07PM +0530, Ajit Agarwal wrote:
> This is the patch-1 for improving ree pass for rs6000 target.
It actually just enables it :-)
The mail body should be the
gcc/
* config/xtensa/xtensa-opts.h: New header.
* config/xtensa/xtensa.h (STRICT_ALIGNMENT): Redefine as
xtensa_strict_align.
* config/xtensa/xtensa.cc (xtensa_option_override): When
-m[no-]strict-align is not specified in the command line set
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New
function.
include/
* xtensa-dynconfig.h (xtensa_config_v4): New struct.
(XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION)
(XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)
Hello All:
This is patch-4 to improve ree pass for rs6000 target.
Use ABI interfaces support.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
ree: Improve ree pass for rs6000 target.
For rs6000 target we see redundant zero and sign
extension
Hello All:
This is patch-3 to improve ree pass for rs6000 target.
Main functionality routines to imprve ree pass.
Bootstrapped and regtested on powerpc64-gnu-linux.
Thanks & Regards
Ajit
ree: Improve ree pass for rs6000 target.
For rs6000 target we see redundant zero and sign
Hello All:
This is the patch-2 to improve ree pass for rs6000 target.
Bootstrapped and regtested on powerpc64-gnu-linux.
Thanks & Regards
Ajit
ree: Improve ree pass for rs6000 target.
For rs6000 target we see redundant zero and sign
extension and done to improve ree
Hello All:
This is the patch-1 for improving ree pass for rs6000 target.
Bootstrapped and regtested on powerpc64-linux-gnu.
Thanks & Regards
Ajit
ree: Improve ree pass for rs6000 target.
Add ree pass as a default pass for rs6000 target.
2023-04-19 Ajit Kumar Agarwal
> From: Hans-Peter Nilsson
> Date: Wed, 19 Apr 2023 06:06:27 +0200
>
> Patch retracted, at least temporarily. My "understanding"
> may be clouded by looking at an actual bug. Sigh.
Mea culpa. I was looking at the result of one
define_peephole2 and thinking it was due to another, and
also
On Wed, Apr 19, 2023 at 12:52:50PM -0400, Jason Merrill wrote:
> On 4/19/23 12:05, Patrick Palka wrote:
> > On Wed, 19 Apr 2023, Patrick Palka wrote:
> >
> > > Aside from correcting how try_class_unification copies multi-dimensional
> > > 'targs', r13-377-g3e948d645bc908 also made it ggc_free
On Wed, Apr 19, 2023 at 12:48:42PM -0400, Jason Merrill wrote:
> On 4/19/23 11:26, Jakub Jelinek wrote:
> > On Wed, Apr 19, 2023 at 11:20:09AM -0400, Jason Merrill wrote:
> > > When I was backporting the earlier 108099 patch I finally saw your
> > > comments on
> > > the PR about the meaning of
On 4/19/23 12:05, Patrick Palka wrote:
On Wed, 19 Apr 2023, Patrick Palka wrote:
Aside from correcting how try_class_unification copies multi-dimensional
'targs', r13-377-g3e948d645bc908 also made it ggc_free this copy as an
optimization. But this is potentially wrong since the call to unify
On 4/19/23 11:26, Jakub Jelinek wrote:
On Wed, Apr 19, 2023 at 11:20:09AM -0400, Jason Merrill wrote:
When I was backporting the earlier 108099 patch I finally saw your comments on
the PR about the meaning of this pattern with the patch being wrong (and a
regression from 11). This fixes that
Sorry for sending messy patches.
Ignore those messy patches and these following patches are the real patches:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616222.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616225.html
LLM, machine learning and AI likes coding with data types that are weird,
float16, bf16, 8 bit float and 4 bit floats. Longer term, would be nice to
natively support these everywhere. Would be nice to trial run them in the
compiler, sort it all out, so that the implementation experience can
From: Ju-Zhe Zhong
This patch adds sanity tests for basic enabling auto-vectorization.
We should make sure compiler enable auto-vectorization strictly according
to '-march'
For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization.
Since SEW = 64 RVV instructions are illegal
From: Ju-Zhe Zhong
This patch is adding 2 compile option for RVV auto-vectorization.
1. -param=riscv-autovec-preference=
This option is to specify the auto-vectorization approach for RVV.
Currently, we only support scalable and fixed-vlmax.
- scalable means VLA auto-vectorization.
From: Ju-Zhe Zhong
This patch enables auto-vectorization accurately according to '-march'
And add len_load/len_store pattern.
For example, for -march=rv32gc_zve32x, we should allow SEW = 64 RVV
auto-vectorization.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode):
From: Ju-Zhe Zhong
PATCH 1: Add compile option for RVV auto-vectorization.
PATCH 2: Enable basic RVV auto-vectorization.
PATCH 3: Add sanity testcases.
*** BLURB HERE ***
Ju-Zhe Zhong (3):
RISC-V: Add auto-vectorization compile option for RVV
RISC-V: Enable basic auto-vectorization for RVV
Ok to cherrypick for 12? It is in GCC 13 and fixes an
annoying ICE.
Martin
Here is a fix for PR105660.
Bootstrapped and regression tested on x86-64.
Fix ICE related to implicit access attributes for VLA arguments [PR105660]
When constructing the specifier string when
From: Ju-Zhe Zhong
This patch adds sanity tests for basic enabling auto-vectorization.
We should make sure compiler enable auto-vectorization strictly according
to '-march'
For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization.
Since SEW = 64 RVV instructions are illegal
From: Ju-Zhe Zhong
This patch adds sanity tests for basic enabling auto-vectorization.
We should make sure compiler enable auto-vectorization strictly according
to '-march'
For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization.
Since SEW = 64 RVV instructions are illegal
From: Ju-Zhe Zhong
This patch is adding 2 compile option for RVV auto-vectorization.
1. -param=riscv-autovec-preference=
This option is to specify the auto-vectorization approach for RVV.
Currently, we only support scalable and fixed-vlmax.
- scalable means VLA auto-vectorization.
From: Ju-Zhe Zhong
This patch enables auto-vectorization accurately according to '-march'
And add len_load/len_store pattern.
For example, for -march=rv32gc_zve32x, we should allow SEW = 64 RVV
auto-vectorization.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode):
From: Ju-Zhe Zhong
PATCH 1: Add compile option for RVV auto-vectorization.
PATCH 2: Enable basic RVV auto-vectorization.
PATCH 3: Add sanity testcases.
*** BLURB HERE ***
Ju-Zhe Zhong (3):
RISC-V: Add auto-vectorization compile option for RVV
RISC-V: Enable basic auto-vectorization for RVV
From: Ju-Zhe Zhong
This patch is adding 2 compile option for RVV auto-vectorization.
1. -param=riscv-autovec-preference=
This option is to specify the auto-vectorization approach for RVV.
Currently, we only support scalable and fixed-vlmax.
- scalable means VLA auto-vectorization.
From: Ju-Zhe Zhong
This patch enables auto-vectorization accurately according to '-march'
And add len_load/len_store pattern.
For example, for -march=rv32gc_zve32x, we should allow SEW = 64 RVV
auto-vectorization.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode):
From: Ju-Zhe Zhong
PATCH 1: Add compile option for RVV auto-vectorization.
PATCH 2: Enable basic RVV auto-vectorization.
PATCH 3: Add sanity testcases.
*** BLURB HERE ***
Ju-Zhe Zhong (3):
RISC-V: Add auto-vectorization compile option for RVV
RISC-V: Enable basic auto-vectorization for RVV
On 4/19/23 17:14, Bernhard Reutner-Fischer via Gcc-patches wrote:
On Wed, 19 Apr 2023 at 03:03, Jerry D via Fortran wrote:
On 4/18/23 12:39 PM, Harald Anlauf via Fortran wrote:
Dear all,
the attached patch adjusts the scan-tree-dump patterns of the
reported testcases which likely were run
The backend pattern for storing a pair of identical values in 32 and
64-bit modes with the machine instruction STP was missing, and
multiple instructions were needed to reproduce this behavior as a
result of failed RTL pattern match in the combine pass.
For the test case:
typedef long long v2di
On Wed, 19 Apr 2023, Patrick Palka wrote:
> Aside from correcting how try_class_unification copies multi-dimensional
> 'targs', r13-377-g3e948d645bc908 also made it ggc_free this copy as an
> optimization. But this is potentially wrong since the call to unify
> within might've captured the args
On 4/19/23 07:51, Frederik Harwath wrote:
Hi Sandra,
the OMP_FOR documentation says that the loop index variable
must be signed and it does not list "!=" in the allowed conditional
expressions. But there is nothing that would automatically cast an
unsigned variable
to signed or that converts
I'll commit this as obvious, so it doesn't trick anyone else
anymore.
-- >8 --
* recog.cc (peep2_attempt, peep2_update_life): Correct
head-comment description of parameter match_len.
---
gcc/recog.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Aside from correcting how try_class_unification copies multi-dimensional
'targs', r13-377-g3e948d645bc908 also made it ggc_free this copy as an
optimization. But this is potentially wrong since the call to unify
within might've captured the args in persistent memory such as the
satisfaction cache
On Wed, Apr 19, 2023 at 11:20:09AM -0400, Jason Merrill wrote:
> When I was backporting the earlier 108099 patch I finally saw your comments on
> the PR about the meaning of this pattern with the patch being wrong (and a
> regression from 11). This fixes that regression; fixing the broader issues
When I was backporting the earlier 108099 patch I finally saw your comments on
the PR about the meaning of this pattern with the patch being wrong (and a
regression from 11). This fixes that regression; fixing the broader issues can
wait.
Tested x86_64-pc-linux-gnu, OK for 13.1 or wait for 13.2?
Committed, thanks :)
On Wed, Apr 19, 2023 at 5:19 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch aligned the MODE_CLASS condition of the IOR to the AND. Then
> more MODE_CLASS besides SCALAR_INT can able to perform the optimization
> A | (~A) -> -1 similar to AND operator. For
Committed to trunk, thanks!
On Wed, Apr 19, 2023 at 8:34 PM wrote:
>
> From: Juzhe-Zhong
>
> RISC-V has provide different VLEN configuration by different ISA
> extension like `zve32x`, `zve64x` and `v`
> zve32x just guarantee the minimal VLEN is 32 bits,
> zve64x guarantee the minimal VLEN is
On Wed, 19 Apr 2023 at 03:03, Jerry D via Fortran wrote:
>
> On 4/18/23 12:39 PM, Harald Anlauf via Fortran wrote:
> > Dear all,
> >
> > the attached patch adjusts the scan-tree-dump patterns of the
> > reported testcases which likely were run in a location such
> > that a path in an error
> On Wed, 19 Apr 2023 06:53:51 PDT (-0700), kito.ch...@sifive.com wrote:
> > ---
> > htdocs/gcc-13/changes.html | 31 ++-
> > 1 file changed, 30 insertions(+), 1 deletion(-)
> >
> > diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> > index
Following code:
typedef __SIZE_TYPE__ size_t;
struct S1s
{
char pad1;
char val;
short pad2;
};
extern char ts[256];
_Bool foo (struct S1s a, size_t i)
{
return (ts[i] > a.val);
}
compiles with -O2 to:
movl%edi, %eax
movsbl %ah, %edi
cmpb%dil, ts(%rsi)
On Wed, 19 Apr 2023 at 14:51, Bernhard Reutner-Fischer
wrote:
>
> On 19 April 2023 09:06:28 CEST, Lipeng Zhu via Fortran
> wrote:
>
> >+#ifdef __GTHREAD_RWLOCK_INIT
> >+#define RWLOCK_DEBUG_ADD(rwlock) do { \
> >+aio_rwlock_debug *n; \
> >+n = malloc
Hi all,
I noticed these define_expand are almost identical modulo some string
substitutions.
This patch compresses them together with a couple of code iterators.
No functional change intended.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
On Wed, 19 Apr 2023 06:53:51 PDT (-0700), kito.ch...@sifive.com wrote:
---
htdocs/gcc-13/changes.html | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index f6941534..5427f805 100644
---
LGTM。
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-04-19 21:53
To: gcc-patches; kito.cheng; palmer; juzhe.zhong; jeffreyalaw
CC: Kito Cheng
Subject: [wwwdocs] gcc-13: Add release note for RISC-V
---
htdocs/gcc-13/changes.html | 31 ++-
1 file changed, 30
---
htdocs/gcc-13/changes.html | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index f6941534..5427f805 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -636,9
Hi Sandra,
the OMP_FOR documentation says that the loop index variable
must be signed and it does not list "!=" in the allowed conditional
expressions. But there is nothing that would automatically cast an
unsigned variable
to signed or that converts the "!=" as you can see from the dump
for
The following makes sure to use solve_add_graph_edge and honoring
special-cases, especially edges from escaped, in the remaining places
the solver adds edges.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
* tree-ssa-structalias.cc (do_ds_constraint): Use
Split out a worker with all the special-casings when adding a graph
edge during solving.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
* tree-ssa-structalias.cc (solve_add_graph_edge): New function,
split out from ...
(do_sd_constraint): ... here.
---
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (valid_type): Adapt for tuple
type support.
(inttype): Ditto.
(floattype): Ditto.
(main): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc: Ditto.
*
On 19 April 2023 09:06:28 CEST, Lipeng Zhu via Fortran
wrote:
>+#ifdef __GTHREAD_RWLOCK_INIT
>+#define RWLOCK_DEBUG_ADD(rwlock) do { \
>+aio_rwlock_debug *n; \
>+n = malloc (sizeof(aio_rwlock_debug));\
My malloc can fail.
>+n->prev =
From: Juzhe-Zhong
RISC-V has provide different VLEN configuration by different ISA
extension like `zve32x`, `zve64x` and `v`
zve32x just guarantee the minimal VLEN is 32 bits,
zve64x guarantee the minimal VLEN is 64 bits,
and v guarantee the minimal VLEN is 128 bits,
Current status (without
On Wed, Apr 19, 2023 at 2:20 PM Prathamesh Kulkarni
wrote:
>
> On Wed, 19 Apr 2023 at 16:17, Richard Biener
> wrote:
> >
> > On Wed, Apr 19, 2023 at 11:21 AM Prathamesh Kulkarni
> > wrote:
> > >
> > > On Tue, 11 Apr 2023 at 19:36, Prathamesh Kulkarni
> > > wrote:
> > > >
> > > > On Tue, 11
From: Juzhe-Zhong
RISC-V has provide different VLEN configuration by different ISA
extension like `zve32x`, `zve64x` and `v`
zve32x just guarantee the minimal VLEN is 32 bits,
zve64x guarantee the minimal VLEN is 64 bits,
and v guarantee the minimal VLEN is 128 bits,
Current status (without
On 4/18/23 18:40, Aldy Hernandez wrote:
I will push this when a final round of testing finishes on x86-64 Linux.
gcc/ChangeLog:
* value-range.h (Value_Range::Value_Range): Avoid pointer sharing.
---
gcc/value-range.h | 13 -
1 file changed, 12 insertions(+), 1
On Wed, 19 Apr 2023 at 10:36, Richard Biener wrote:
>
> The following picks up the coccinelle generated patch from Bernhard,
> leaving out the fortran frontend parts and fixing up the rest.
> In particular both gmp.h and mpfr.h contain macros like
> #define mpfr_inf_p(_x) ((_x)->_mpfr_exp
Could you add more description? maybe like this:
RISC-V has provide different VLEN configuration by different ISA
extension like `zve32x`, `zve64x` and `v`
zve32x just guarantee the minimal VLEN is 32 bits,
zve64x guarantee the minimal VLEN is 64 bits,
and v guarantee the minimal VLEN is 128
On Wed, 19 Apr 2023 at 16:17, Richard Biener wrote:
>
> On Wed, Apr 19, 2023 at 11:21 AM Prathamesh Kulkarni
> wrote:
> >
> > On Tue, 11 Apr 2023 at 19:36, Prathamesh Kulkarni
> > wrote:
> > >
> > > On Tue, 11 Apr 2023 at 14:17, Richard Biener
> > > wrote:
> > > >
> > > > On Wed, Apr 5, 2023
The following makes sure to remove the copy edges we ignore or
need to special-case only once.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
* tree-ssa-structalias.cc (solve_graph): Remove self-copy
edges, remove edges from escaped after special-casing them.
---
The following fixes the escape special casing to test the proper
variable IDs.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
* tree-ssa-structalias.cc (do_sd_constraint): Fixup escape
special casing.
---
gcc/tree-ssa-structalias.cc | 2 +-
1 file changed, 1
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
* tree-ssa-structalias.cc (do_sd_constraint): Do not write
to the LHS varinfo solution member.
---
gcc/tree-ssa-structalias.cc | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
Since we do not update successor edges when merging nodes we have
to deal with this in the users. The following avoids putting those
on the topo order vector.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
* tree-ssa-structalias.cc (topo_visit): Look at the real
The following removes a special case to not merge a block with
only a non-local label. We have a restriction of non-local labels
to be the first statement (and label) in a block, but otherwise nothing,
if the last stmt of A is a non-local label then it will be still
the first statement of the
Update the Patch v2 for more detail information for clarification. Please help
to review continuously.
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616175.html
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 19, 2023 6:33 PM
To: Kito Cheng ; juzhe.zh...@rivai.ai
From: Pan Li
This patch try to adjust the RISC-V Vector RTL for the
generic shortcut optimization for RVV integer compare.
It includes compare operator eq, ne, ltu, lt, leu, le,
gtu, gt, geu and ge.
Assume we have below test code.
vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1,
On Tue, Apr 18, 2023 at 12:23 PM Tamar Christina via Gcc-patches
wrote:
>
> Hi All,
>
> Following on from Richi's RFC[1] this is another attempt to split up match.pd
> into multiple gimple-match and generic-match files. This version is fully
> automated and requires no human intervention.
>
>
On Wed, Apr 19, 2023 at 11:21 AM Prathamesh Kulkarni
wrote:
>
> On Tue, 11 Apr 2023 at 19:36, Prathamesh Kulkarni
> wrote:
> >
> > On Tue, 11 Apr 2023 at 14:17, Richard Biener
> > wrote:
> > >
> > > On Wed, Apr 5, 2023 at 10:39 AM Prathamesh Kulkarni via Gcc-patches
> > > wrote:
> > > >
> > >
Thanks Jeff.
Address Jeff's comment and resend fix patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616170.html
This patch also added a testcase coming from Kito (Kito reduced google/highway
testcase from over 10W lines codes into 100 lines codes!!!).
juzhe.zh...@rivai.ai
From:
> -Original Message-
> From: Richard Biener
> Sent: Tuesday, April 18, 2023 11:48 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; rguent...@suse.de;
> j...@ventanamicro.com
> Subject: Re: [PATCH 2/3]middle-end match.pd: simplify debug dump checks
>
> On Tue, Apr 18, 2023 at
From: Ju-Zhe Zhong
Testcase coming from Kito.
Co-authored-by: kito-cheng
Co-authored-by: kito-cheng
PR 109535
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function.
(pass_vsetvl::cleanup_insns): Fix bug.
gcc/testsuite/ChangeLog:
From: Ju-Zhe Zhong
PR 109535
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function.
(pass_vsetvl::cleanup_insns): Fix bug.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/pr109535.C: New test.
*
Sure thing.
For Changlog, I consider it was generated automatically in previous. LOL.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, April 19, 2023 5:46 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ;
Kito.cheng ; Wang, Yanzhang
Subject: Re: Re: [PATCH] RISC-V:
CFG cleanup maintains BB_FORWARDER_BLOCK and uses FORWARDER_BLOCK_P
to check that apart from two places which use forwarder_block_p
in outgoing_edges_match alongside many BB_FORWARDER_BLOCK uses.
The following adjusts those.
Bootstrapped and tested on x86_64-unknown-linux-gnu, I verified
On Wed, 2023-04-19 at 11:03 +0800, Lulu Cheng wrote:
/* snip */
> > +loongarch_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT
> > length,
> > + HOST_WIDE_INT delta)
> > {
> > - HOST_WIDE_INT offset, delta;
> > - unsigned HOST_WIDE_INT bits;
> > +
On Tue, 2023-04-18 at 20:03 +0800, Lulu Cheng wrote:
>
> 在 2023/4/18 下午7:48, Xi Ruoyao 写道:
> > On Tue, 2023-04-18 at 19:21 +0800, Lulu Cheng wrote:
> > > 在 2023/4/18 下午5:27, Xi Ruoyao 写道:
> > > > On Mon, 2023-04-10 at 17:45 +0800, Lulu Cheng wrote:
> > > > > Sorry, it's my question. I still have
On Wed, Apr 19, 2023 at 1:33 AM Andrew Pinski via Gcc-patches
wrote:
>
> After a phiopt change, I got a failure of cmov9.c.
> The RTL IR has zero_extend on the outside of
> the if_then_else rather than on the side. Both
> ways are considered canonical as mentioned in
> PR 66588.
>
> This fixes
This patch adds the 'Zfa' extension for riscv, which is based on:
https://github.com/riscv/riscv-isa-manual/commits/zfb
https://github.com/riscv/riscv-isa-manual/commit/1f038182810727f5feca311072e630d6baac51da
The binutils-gdb for 'Zfa' extension:
The following simplifies and outlines gimple_assign_load. In
particular it is not necessary to get at the base of the possibly
loaded expression but just handle the case of a single handled
component wrapping a non-memory operand.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
HI JuZhe:
Thanks for explaining!
Hi Pan:
I think that would be helpful if JuZhe's explaining that could be
written into the commit log.
> gcc/ChangeLog:
>
>* config/riscv/riscv-v.cc (emit_pred_op):
>* config/riscv/riscv-vector-builtins-bases.cc:
>*
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